ngspice/examples/xspice/verilator/adc.cir

Simulation of a switched-capacitor SAR ADC with Verilator and d_cosim

* Model line for the digital control implemented by Verilator.

.model dut d_cosim simulation="./adc"

* The bulk of the circuit is in a shared file.

.include adc.shared
.end
Add the support files for co-simulation with Verilog code compiled by Verilator. Also add script files to Visual Studio builds that are already installed by the Makefile builds. 2023-11-27 19:02:10 +01:00			`Simulation of a switched-capacitor SAR ADC with Verilator and d_cosim`

Add additional examples of Verilog co-simulation and share the Verilog source and large parts of the example circuits between Verilator and Icarus Verilog. Verilog source file adc.v has improved style: all assignments in the always block are now non-blocking. 2024-06-10 12:40:37 +02:00			`* Model line for the digital control implemented by Verilator.`
Add the support files for co-simulation with Verilog code compiled by Verilator. Also add script files to Visual Studio builds that are already installed by the Makefile builds. 2023-11-27 19:02:10 +01:00
Add additional examples of Verilog co-simulation and share the Verilog source and large parts of the example circuits between Verilator and Icarus Verilog. Verilog source file adc.v has improved style: all assignments in the always block are now non-blocking. 2024-06-10 12:40:37 +02:00			`.model dut d_cosim simulation="./adc"`
Add the support files for co-simulation with Verilog code compiled by Verilator. Also add script files to Visual Studio builds that are already installed by the Makefile builds. 2023-11-27 19:02:10 +01:00
Add additional examples of Verilog co-simulation and share the Verilog source and large parts of the example circuits between Verilator and Icarus Verilog. Verilog source file adc.v has improved style: all assignments in the always block are now non-blocking. 2024-06-10 12:40:37 +02:00			`* The bulk of the circuit is in a shared file.`
Add the support files for co-simulation with Verilog code compiled by Verilator. Also add script files to Visual Studio builds that are already installed by the Makefile builds. 2023-11-27 19:02:10 +01:00
Add additional examples of Verilog co-simulation and share the Verilog source and large parts of the example circuits between Verilator and Icarus Verilog. Verilog source file adc.v has improved style: all assignments in the always block are now non-blocking. 2024-06-10 12:40:37 +02:00			`.include adc.shared`
Add the support files for co-simulation with Verilog code compiled by Verilator. Also add script files to Visual Studio builds that are already installed by the Makefile builds. 2023-11-27 19:02:10 +01:00			`.end`