ngspice/examples/xspice/icarus_verilog/delay.cir

* Waveform generation by Verilog delays

adut null [ d4 d3 d2 d1 d0 ] ring
.model ring d_cosim simulation="ivlng" sim_args = [ "delay" ]

.control
tran 20u 100u
plot d4 d3 d2 d1 d0 digitop
.endc
.end
Add additional examples of Verilog co-simulation and share the Verilog source and large parts of the example circuits between Verilator and Icarus Verilog. Verilog source file adc.v has improved style: all assignments in the always block are now non-blocking. 2024-06-10 12:40:37 +02:00			`* Waveform generation by Verilog delays`

			`adut null [ d4 d3 d2 d1 d0 ] ring`
			`.model ring d_cosim simulation="ivlng" sim_args = [ "delay" ]`

			`.control`
			`tran 20u 100u`
			`plot d4 d3 d2 d1 d0 digitop`
			`.endc`
			`.end`