ngspice/examples/xspice/icarus_verilog/555.cir

Verilog-controlled simple timer.

* This is the model for an RS flip-flop implemented by Icarus Verilog.

.model vlog_ff d_cosim simulation="ivlng" sim_args=["555"]

* The bulk of the circuit is in a shared file.

.include ../verilator/555.shared
.end
Add additional examples of Verilog co-simulation and share the Verilog source and large parts of the example circuits between Verilator and Icarus Verilog. Verilog source file adc.v has improved style: all assignments in the always block are now non-blocking. 2024-06-10 12:40:37 +02:00			`Verilog-controlled simple timer.`

			`* This is the model for an RS flip-flop implemented by Icarus Verilog.`

			`.model vlog_ff d_cosim simulation="ivlng" sim_args=["555"]`

			`* The bulk of the circuit is in a shared file.`

			`.include ../verilator/555.shared`
			`.end`