63 lines
1.5 KiB
VHDL
63 lines
1.5 KiB
VHDL
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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entity adc is
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generic ( Bits : integer := 6 );
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port (
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Clk : in std_logic;
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Comp : in std_logic;
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Start : in std_logic;
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Sample : out std_logic;
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Done : out std_logic;
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Result : out unsigned(0 to Bits - 1)
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);
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end entity;
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architecture ghdl_adc of adc is
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signal SR : unsigned(0 to Bits - 1);
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signal Result_Reg : unsigned(0 to Bits - 1);
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signal Sample_Reg : std_logic := '0';
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signal Running : std_logic := '0';
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begin
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Result <= Result_Reg;
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Sample <= Sample_Reg;
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process (Clk)
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constant Zeros : unsigned(0 to Bits - 1) := (others => '0');
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variable NextSR : unsigned(0 to Bits - 1);
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begin
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if rising_edge(Clk) then
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if Running = '1' then
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if Sample_Reg = '1' then
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Sample_Reg <= '0';
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SR(Bits - 1) <= '1';
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Result_Reg(Bits - 1) <= '1';
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else
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if SR /= 0 then
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NextSR := shift_left(SR, 1);
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if Comp = '1' then
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Result_Reg <= (Result_Reg and not SR) or NextSR;
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else
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Result_Reg <= Result_Reg or NextSR;
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end if;
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SR <= NextSR;
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else
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Running <= '0';
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Done <= '1';
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end if;
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end if;
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else
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if Start = '1' then
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Running <= '1';
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Sample_Reg <= '1';
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Done <= '0';
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SR <= Zeros;
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Result_Reg <= Zeros;
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end if;
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end if;
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end if;
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end process;
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end architecture;
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