30 lines
581 B
VHDL
30 lines
581 B
VHDL
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-- Very simple logic for a 555 timer simulation
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library ieee;
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use ieee.std_logic_1164.all;
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entity timer_core is
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port (
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Trigger, Threshold, Reset : in std_logic;
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Q, Qbar : out std_logic
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);
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end timer_core;
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architecture rtl of timer_core is
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signal result : std_logic := '0';
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signal ireset, go : std_logic;
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begin
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go <= Trigger and Reset;
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ireset <= (Threshold and not go) or not Reset;
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Q <= result;
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Qbar <= not result;
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process (go, ireset)
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begin
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if rising_edge(go) or rising_edge(ireset) then
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result <= go;
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end if;
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end process;
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end rtl;
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