44 lines
1.0 KiB
SourcePawn
44 lines
1.0 KiB
SourcePawn
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Simple regulated DCDC step-up converter
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V1 clock 0 PULSE(0 6 0 19u 1u 10n 20.01u)
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V2 ref 0 2.5
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R1 OUT outdiv 100K
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R2 0 outdiv 27k
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R3 outdiv x 10k
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C2 err x 50n
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B1 err 0 V = max(0,min(5,V(ref,x)*10k))
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B2 gate 0 V = max(0,min(5,V(err,clock)*1k))
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V3 +V 0 5.0
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L1 +V lx 220u
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RL lx out1 125m
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M1 out1 gate 0 IRF510
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D1 out1 OUT MBRS340
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C1 OUT cx 33u
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RC cx 0 50m
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R4 out2 OUT R = (time<12ms ? {Rload} : time<20ms ? {Rload/2} : {2*Rload})
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V4 out2 0 0.0
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.param Rload=100
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.model IRF510 VDMOS nchan
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+ Vto=3.6 Kp=1.3 Lambda=.001 Theta=0.07 ksubthres=.1
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+ Rg=3 Rd=200m Rs=54m Rds=1e7
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+ Cgdmax=.2n Cgdmin=.05n a=0.3 Cgs=.12n
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+ Is=17p N=1.1 Rb=80m XTI=3
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+ Cjo=.25n Vj=0.8 m=0.5
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+ tcvth=0.007 MU=-1.27 texp0=1.5
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.model MBRS340 D(Is=22.6u Rs=.042 N=1.094 Cjo=480p M=.61 Eg=.69 Xti=2)
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.control
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listing e
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option method=gear
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tran 10n 30m 0 5n
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* write dcdc.raw
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plot v(err) v(clock) v(gate) v(out)
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plot -i(V3) i(V4) ylimit 0 1
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rusage all
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.endc
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.end
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