2022-07-31 15:49:50 +02:00
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.probe test with simple CMOS inverter, many buggy .probe commands
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2021-11-28 17:18:50 +01:00
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Vd dd 0 dc 5
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Vin in 0 dc 0 PULSE (0 5 0 10n 10n 100n 200n)
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Vs ss 0 dc 0
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mn1 out in ss ss nm
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mp1 out in dd dd pm
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.model nm nmos
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.model pm pmos
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*.dc vin 0 5 0.1
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.tran 5n 500n
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* inputs o.k.
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2021-12-13 17:06:24 +01:00
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.probe i(mp1:s) i(mn1:s) v(in) v(out) vd(mn1:d:s) vd(mp1:1, mn1:1) vd(mn1:1:0)
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2021-11-28 17:18:50 +01:00
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2021-12-13 17:06:24 +01:00
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* buggy inputs (to check the error messages)
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2021-11-29 11:11:58 +01:00
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.probe i(mn1:z) vd(mp1:0:0) vd(mp1:1:1) hhhh) i(:u) VD(z) i(()) vd(:0:0) i(:z)
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2021-11-28 17:18:50 +01:00
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.save @mn1[id]
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.control
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run
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display
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set xbrushwidth=2
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*plot commands o.k.
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plot i(mn1:s) i(mp1:s)
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2021-12-13 17:06:24 +01:00
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*buggy plot command
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2021-11-28 17:18:50 +01:00
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plot i(mp1:8)
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2021-12-13 17:06:24 +01:00
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* plot o.k.
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2021-11-28 17:18:50 +01:00
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plot in out
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plot @mn1[id] - i(mn1:s)
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.endc
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.end
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