ngspice/tests/bsim3soi/inv_dc.cir

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2009-04-19 12:20:00 +02:00
B4SOI Drain Gate Source Back-gate(substrate) Body Tx W L (body ommitted for FB)
* Modified by Darsen Lu 03/11/2009
2008-04-20 11:36:53 +02:00
2010-02-21 14:44:19 +01:00
.include ./nmos4p3.mod
.include ./pmos4p3.mod
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.option TEMP=27C noacct
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Vpower VD 0 1.5
Vgnd VS 0 0
Vgate Gate 0 0.0
MN0 VS Gate Out VS N1 W=10u L=0.18u
MP0 VD Gate Out VS P1 W=20u L=0.18u
.dc Vgate 0 1.5 0.05
.print dc v(out)
.END