ngspice/examples/xspice/icarus_verilog/pwm.cir

* Waveform generation by PWM in Verilog

adut null [ out ] pwm_sin
.model pwm_sin d_cosim simulation="ivlng" sim_args = [ "pwm" ]

r1 out smooth 100k
c1 smooth 0 1u
.control
tran 1m 2
plot out-3.3 smooth
.endc
.end
Add additional examples of Verilog co-simulation and share the Verilog source and large parts of the example circuits between Verilator and Icarus Verilog. Verilog source file adc.v has improved style: all assignments in the always block are now non-blocking. 2024-06-10 12:40:37 +02:00			`* Waveform generation by PWM in Verilog`

			`adut null [ out ] pwm_sin`
			`.model pwm_sin d_cosim simulation="ivlng" sim_args = [ "pwm" ]`

			`r1 out smooth 100k`
			`c1 smooth 0 1u`
			`.control`
			`tran 1m 2`
			`plot out-3.3 smooth`
			`.endc`
			`.end`