ngspice/examples/xspice/icarus_verilog/adc.cir

Simulation of a switched-capacitor SAR ADC with Verilator and d_cosim

* Model line for the digital control implemented by Icarus Verilog.

.model dut d_cosim simulation="ivlng" sim_args=["adc"]

* The bulk of the circuit is in a shared file.

.include ../verilator/adc.shared
.end
Add additional examples of Verilog co-simulation and share the Verilog source and large parts of the example circuits between Verilator and Icarus Verilog. Verilog source file adc.v has improved style: all assignments in the always block are now non-blocking. 2024-06-10 12:40:37 +02:00			`Simulation of a switched-capacitor SAR ADC with Verilator and d_cosim`

			`* Model line for the digital control implemented by Icarus Verilog.`

			`.model dut d_cosim simulation="ivlng" sim_args=["adc"]`

			`* The bulk of the circuit is in a shared file.`

			`.include ../verilator/adc.shared`
			`.end`