2018-05-18 15:58:45 +02:00
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Test of VDMOS gate-source and gate-drain capacitance
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2018-12-22 22:16:03 +01:00
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m1 d g s IXTP6N100D2
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2018-05-18 15:58:45 +02:00
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2018-12-22 22:16:03 +01:00
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.MODEL IXTP6N100D2 VDMOS(KP=2.9 RS=0.1 RD=1.3 RG=1 VTO=-2.7 LAMBDA=0.03 CGDMAX=3000p CGDMIN=2p CGS=2915p a=1 TT=1371n IS=2.13E-08 N=1.564 RB=0.0038 m=0.548 Vj=0.1 Cjo=3200pF ksubthres=0.1)
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2018-05-18 15:58:45 +02:00
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vd d 0 dc 5
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vg g 0 pwl (0 -3 1 3)
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vs s 0 0
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.control
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save all @m1[cgd] @m1[cgs]
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tran 1m 1
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plot vs#branch
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plot @m1[cgd] @m1[cgs]
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.endc
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.end
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