67 lines
2.0 KiB
Plaintext
67 lines
2.0 KiB
Plaintext
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ADDER - 4 BIT ALL-NAND-GATE BINARY ADDER
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*** SUBCIRCUIT DEFINITIONS
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.SUBCKT NAND in1 in2 out VDD
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* NODES: INPUT(2), OUTPUT, VCC
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M1 out in2 Vdd Vdd p1 W=7.5u L=0.35u pd=13.5u ad=22.5p ps=13.5u as=22.5p
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M2 net.1 in2 0 0 n1 W=3u L=0.35u pd=9u ad=9p ps=9u as=9p
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M3 out in1 Vdd Vdd p1 W=7.5u L=0.35u pd=13.5u ad=22.5p ps=13.5u as=22.5p
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M4 out in1 net.1 0 n1 W=3u L=0.35u pd=9u ad=9p ps=9u as=9p
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.ENDS NAND
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.SUBCKT ONEBIT 1 2 3 4 5 6
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* NODES: INPUT(2), CARRY-IN, OUTPUT, CARRY-OUT, VCC
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X1 1 2 7 6 NAND
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X2 1 7 8 6 NAND
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X3 2 7 9 6 NAND
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X4 8 9 10 6 NAND
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X5 3 10 11 6 NAND
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X6 3 11 12 6 NAND
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X7 10 11 13 6 NAND
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X8 12 13 4 6 NAND
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X9 11 7 5 6 NAND
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.ENDS ONEBIT
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.SUBCKT TWOBIT 1 2 3 4 5 6 7 8 9
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* NODES: INPUT - BIT0(2) / BIT1(2), OUTPUT - BIT0 / BIT1,
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* CARRY-IN, CARRY-OUT, VCC
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X1 1 2 7 5 10 9 ONEBIT
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X2 3 4 10 6 8 9 ONEBIT
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.ENDS TWOBIT
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.SUBCKT FOURBIT 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
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* NODES: INPUT - BIT0(2) / BIT1(2) / BIT2(2) / BIT3(2),
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* OUTPUT - BIT0 / BIT1 / BIT2 / BIT3, CARRY-IN, CARRY-OUT, VCC
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X1 1 2 3 4 9 10 13 16 15 TWOBIT
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X2 5 6 7 8 11 12 16 14 15 TWOBIT
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.ENDS FOURBIT
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*** POWER
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VCC 99 0 DC 3.3V
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*** ALL INPUTS
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VIN1A 1 0 DC 0 PULSE(0 3 0 5NS 5NS 20NS 50NS)
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VIN1B 2 0 DC 0 PULSE(0 3 0 5NS 5NS 30NS 100NS)
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VIN2A 3 0 DC 0 PULSE(0 3 0 5NS 5NS 50NS 200NS)
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VIN2B 4 0 DC 0 PULSE(0 3 0 5NS 5NS 90NS 400NS)
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VIN3A 5 0 DC 0 PULSE(0 3 0 5NS 5NS 170NS 800NS)
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VIN3B 6 0 DC 0 PULSE(0 3 0 5NS 5NS 330NS 1600NS)
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VIN4A 7 0 DC 0 PULSE(0 3 0 5NS 5NS 650NS 3200NS)
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VIN4B 8 0 DC 0 PULSE(0 3 0 5NS 5NS 1290NS 6400NS)
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*** DEFINE NOMINAL CIRCUIT
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X1 1 2 3 4 5 6 7 8 9 10 11 12 0 13 99 FOURBIT
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.option noinit acct
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.TRAN 500p 6400NS
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* save inputs
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.save V(1) V(2) V(3) V(4) V(5) V(6) V(7) V(8)
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* use BSIM3 model with default parameters
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.model n1 nmos level=49 version=3.3.0
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.model p1 pmos level=49 version=3.3.0
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*.include ./Modelcards/modelcard32.nmos
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*.include ./Modelcards/modelcard32.pmos
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.END
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