31 lines
641 B
Plaintext
31 lines
641 B
Plaintext
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User defined nodes
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*
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* This circuit contains a mix of node types including
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* two 'real' type user-defined nodes and associated
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* node bridges.
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*
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.tran 1e-6 1e-4
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*
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v1 1 0 0.0 pulse(0 1 2e-5)
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r1 1 0 1k
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*
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abridge1 [1] [enable] node_bridge1
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.model node_bridge1 adc_bridge
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*
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aclk [enable clk] clk nand
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.model nand d_nand (rise_delay=1e-5 fall_delay=1e-5)
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*
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abridge2 clk enable real_node1 node_bridge2
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.model node_bridge2 d_to_real (zero=-1 one=1)
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*
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again real_node1 real_node2 times10
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.model times10 real_gain (gain=10)
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*
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abridge3 real_node2 analog_node node_bridge3
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.model node_bridge3 real_to_v
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*
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rout analog_node 0 1k
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*
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*
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.end
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