mirror of https://github.com/YosysHQ/nextpnr.git
218 lines
9.0 KiB
C++
218 lines
9.0 KiB
C++
/*
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* nextpnr -- Next Generation Place and Route
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*
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* Copyright (C) 2024 The Project Peppercorn Authors.
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#include <functional>
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#include <queue>
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#include "gatemate.h"
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#include "log.h"
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#include "nextpnr_assertions.h"
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#define HIMBAECHEL_CONSTIDS "uarch/gatemate/constids.inc"
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#include "himbaechel_constids.h"
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NEXTPNR_NAMESPACE_BEGIN
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namespace {
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struct QueuedWire
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{
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explicit QueuedWire(WireId wire, float delay = 0.0) : wire{wire}, delay{delay} {};
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WireId wire;
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float delay;
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bool operator>(const QueuedWire &rhs) const { return this->delay > rhs.delay; }
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};
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} // namespace
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void GateMateImpl::route_clock()
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{
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auto clk_nets = std::vector<NetInfo *>{};
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auto reserved_wires = dict<WireId, IdString>{};
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auto feeds_clk_port = [](PortRef &port) {
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return port.cell->type.in(id_CPE_HALF, id_CPE_HALF_L, id_CPE_HALF_U) && port.port.in(id_CLK);
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};
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auto pip_plane = [&](PipId pip) {
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const auto &extra_data =
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*reinterpret_cast<const GateMatePipExtraDataPOD *>(chip_pip_info(ctx->chip_info, pip).extra_data.get());
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if (extra_data.type != PipExtra::PIP_EXTRA_MUX)
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return uint8_t{0};
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return extra_data.plane;
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};
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auto reserve = [&](WireId wire, NetInfo *net) {
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if (ctx->debug) {
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auto wire_name = "(uninitialized)";
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if (wire != WireId())
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wire_name = ctx->nameOfWire(wire);
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log_info(" reserving wire %s\n", wire_name);
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}
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reserved_wires.insert({wire, net->name});
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};
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log_info("Routing clock nets...\n");
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for (auto &net_pair : ctx->nets) {
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NetInfo *net = net_pair.second.get();
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if (!net->driver.cell)
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continue;
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bool is_clk_net = false;
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for (auto &usr : net->users) {
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if (feeds_clk_port(usr)) {
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is_clk_net = true;
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auto clk_sink_wire = ctx->getNetinfoSinkWire(net, usr, 0);
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reserve(clk_sink_wire, net);
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auto en_port = usr.cell->ports.find(id_EN);
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if (en_port != usr.cell->ports.end() && en_port->second.net != nullptr) {
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auto en_sink_wire = ctx->getNetinfoSinkWire(
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en_port->second.net, en_port->second.net->users.at(en_port->second.user_idx), 0);
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reserve(en_sink_wire, en_port->second.net);
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}
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auto sr_port = usr.cell->ports.find(id_SR);
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if (sr_port != usr.cell->ports.end() && sr_port->second.net != nullptr) {
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auto sr_sink_wire = ctx->getNetinfoSinkWire(
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sr_port->second.net, sr_port->second.net->users.at(sr_port->second.user_idx), 0);
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reserve(sr_sink_wire, sr_port->second.net);
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}
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}
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}
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if (is_clk_net)
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clk_nets.push_back(net);
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}
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for (auto clk_net : clk_nets) {
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log_info(" routing net '%s'\n", clk_net->name.c_str(ctx));
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ctx->bindWire(ctx->getNetinfoSourceWire(clk_net), clk_net, STRENGTH_LOCKED);
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auto bufg_idx = ctx->getBelLocation(clk_net->driver.cell->bel).z;
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auto clk_plane = 9 + bufg_idx;
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for (auto &usr : clk_net->users) {
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std::priority_queue<QueuedWire, std::vector<QueuedWire>, std::greater<QueuedWire>> visit;
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dict<WireId, PipId> backtrace;
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WireId dest = WireId();
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if (!feeds_clk_port(usr))
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continue;
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auto cpe_loc = ctx->getBelLocation(usr.cell->bel);
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auto is_glb_clk = clk_net->driver.cell->type == id_BUFG;
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auto sink_wire = ctx->getNetinfoSinkWire(clk_net, usr, 0);
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if (ctx->debug) {
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auto sink_wire_name = "(uninitialized)";
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if (sink_wire != WireId())
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sink_wire_name = ctx->nameOfWire(sink_wire);
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log_info(" routing arc to %s.%s (wire %s):\n", usr.cell->name.c_str(ctx), usr.port.c_str(ctx),
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sink_wire_name);
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}
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visit.push(QueuedWire(sink_wire));
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while (!visit.empty()) {
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QueuedWire curr = visit.top();
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visit.pop();
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if (curr.wire == ctx->getNetinfoSourceWire(clk_net)) {
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if (ctx->debug)
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log_info(" (%.3fns)\n", curr.delay);
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dest = curr.wire;
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break;
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}
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PipId bound_pip;
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auto fnd_wire = clk_net->wires.find(curr.wire);
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if (fnd_wire != clk_net->wires.end()) {
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bound_pip = fnd_wire->second.pip;
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}
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for (auto uh : ctx->getPipsUphill(curr.wire)) {
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if (!ctx->checkPipAvailForNet(uh, clk_net))
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continue;
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WireId src = ctx->getPipSrcWire(uh);
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if (backtrace.count(src))
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continue;
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if (!ctx->checkWireAvail(src) && ctx->getBoundWireNet(src) != clk_net)
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continue;
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if (bound_pip != PipId() && uh != bound_pip)
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continue;
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// Has this wire been reserved for another net?
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auto reserved = reserved_wires.find(src);
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if (reserved != reserved_wires.end() && reserved->second != clk_net->name)
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continue;
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auto pip_loc = ctx->getPipLocation(uh);
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// Use only a specific plane to minimise congestion for global clocks.
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if (is_glb_clk && (pip_loc.x != cpe_loc.x || pip_loc.y != cpe_loc.y)) {
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// Plane 9 is the clock plane, so it should only ever use itself.
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if (clk_plane == 9 && pip_plane(uh) != 9)
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continue;
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// Plane 10 is the enable plane.
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// When there's a set/reset, we want to use the switchbox X23 pip to change directly to plane 9.
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if (clk_plane == 10 && pip_plane(uh) != 9 && pip_plane(uh) != 10)
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continue;
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// Plane 11 is the set/reset plane; we want to use the switchbox X14 pip to go to plane 12, then
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// use the IM to switch to plane 9.
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if (clk_plane == 11 && pip_plane(uh) == 10)
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continue;
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// Plane 12 is the spare plane; we can use the IM to change directly to plane 9.
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if (clk_plane == 12 && pip_plane(uh) != 9 && pip_plane(uh) != 12)
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continue;
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}
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backtrace[src] = uh;
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auto delay = ctx->getDelayNS(ctx->getPipDelay(uh).maxDelay() + ctx->getWireDelay(src).maxDelay() +
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ctx->getDelayEpsilon());
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visit.push(QueuedWire(src, curr.delay + delay));
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}
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}
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if (dest == WireId()) {
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log_info(" failed to find a route using dedicated resources. %s -> %s\n",
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clk_net->driver.cell->name.c_str(ctx), usr.cell->name.c_str(ctx));
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}
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while (backtrace.count(dest)) {
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auto uh = backtrace[dest];
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dest = ctx->getPipDstWire(uh);
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if (ctx->getBoundWireNet(dest) == clk_net) {
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NPNR_ASSERT(clk_net->wires.at(dest).pip == uh);
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if (ctx->debug)
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log_info(" pip %s --> %s (plane %hhd)\n", ctx->nameOfPip(uh),
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ctx->nameOfWire(dest), pip_plane(uh));
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} else if (ctx->getBoundWireNet(dest) == nullptr) {
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ctx->bindPip(uh, clk_net, STRENGTH_LOCKED);
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if (ctx->debug)
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log_info(" bind pip %s --> %s (plane %hhd)\n", ctx->nameOfPip(uh),
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ctx->nameOfWire(dest), pip_plane(uh));
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} else {
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log_error("Can't bind pip %s because wire %s is already bound\n", ctx->nameOfPip(uh),
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ctx->nameOfWire(dest));
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}
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if (dest == sink_wire)
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break;
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}
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}
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}
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}
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NEXTPNR_NAMESPACE_END
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