mirror of https://github.com/YosysHQ/nextpnr.git
e73506104b
Configuring K < 4 used to result in "dangling" inputs to the cells being generated (those are just not driven by anything in the resulting Verilog/JSON). Configuring K > 4 used to result in an assertion crash in cells.cc. The ctx.setLutK call fixes both cases. |
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|---|---|---|
| .. | ||
| examples | ||
| synth | ||
| viaduct | ||
| CMakeLists.txt | ||
| arch.cc | ||
| arch.h | ||
| arch_pybindings.cc | ||
| arch_pybindings.h | ||
| archdefs.h | ||
| cells.cc | ||
| cells.h | ||
| chipdb.cc | ||
| main.cc | ||
| pack.cc | ||
| viaduct_api.cc | ||
| viaduct_api.h | ||
| viaduct_constids.h | ||
| viaduct_helpers.cc | ||
| viaduct_helpers.h | ||