nextpnr/himbaechel/uarch/gowin
gatecat a7c3bfe6e6 clangformat
Signed-off-by: gatecat <gatecat@ds0.me>
2026-03-24 19:06:31 +01:00
..
CMakeLists.txt Gowin. Divide packer. (#1645) 2026-02-21 08:11:39 +01:00
constids.inc gowin: add DL-series latch cell support (#1652) 2026-03-14 19:12:08 +00:00
cst.cc Gowin. Ignore empty lines. (#1626) 2026-01-20 08:11:48 +01:00
cst.h gowin: Himbaechel. Add constraint file processing. 2023-08-31 08:28:09 +02:00
globals.cc Gowin. Add GW5AST-138C chip. (#1631) 2026-01-31 13:01:22 +01:00
globals.h gowin: Himbaechel. Add a clock router. 2023-08-31 08:28:09 +02:00
gowin.cc gowin: Add SLICE BELs to gui 2026-03-09 12:36:24 +01:00
gowin.h clangformat 2026-03-24 19:06:31 +01:00
gowin_arch_gen.py gowin: Add timings for BRAM 2026-03-11 15:24:40 +00:00
gowin_utils.cc GOWIN. Fix dual port CE-OCE. 2026-03-09 12:23:01 +01:00
gowin_utils.h GOWIN. Fix dual port CE-OCE. 2026-03-09 12:23:01 +01:00
pack.cc gowin: add DL-series latch cell support (#1652) 2026-03-14 19:12:08 +00:00
pack.h gowin: add DL-series latch cell support (#1652) 2026-03-14 19:12:08 +00:00
pack_bsram.cc GOWIN. BUGFIX. BSRAM port renaming. (#1669) 2026-03-14 20:52:05 +00:00
pack_dsp.cc Gowin. DSP. Refactor port renaming. 2026-03-04 09:04:55 +01:00
pack_io.cc Gowin. Divide packer. (#1645) 2026-02-21 08:11:39 +01:00
pack_iologic.cc Gowin. Divide packer. (#1645) 2026-02-21 08:11:39 +01:00
pack_luts.cc clangformat 2026-03-24 19:06:31 +01:00