mirror of https://github.com/YosysHQ/nextpnr.git
79 lines
2.7 KiB
C++
79 lines
2.7 KiB
C++
/*
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* nextpnr -- Next Generation Place and Route
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*
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* Copyright (C) 2024 The Project Peppercorn Authors.
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#ifndef GATEMATE_PACK_H
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#define GATEMATE_PACK_H
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#include "gatemate.h"
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NEXTPNR_NAMESPACE_BEGIN
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struct GateMatePacker
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{
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GateMatePacker(Context *ctx, GateMateImpl *uarch) : ctx(ctx), uarch(uarch) { h.init(ctx); };
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void pack_io();
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void pack_io_sel();
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void pack_cpe();
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void pack_addf();
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void pack_bufg();
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void sort_bufg();
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void insert_pll_bufg();
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void pack_pll();
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void pack_misc();
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void pack_constants();
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void pack_ram();
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void remove_constants();
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void remove_not_used();
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private:
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void dff_to_cpe(CellInfo *dff, CellInfo *cpe);
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void insert_bufg(CellInfo *cell, IdString port);
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void disconnect_if_gnd(CellInfo *cell, IdString input);
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void pll_out(CellInfo *cell, IdString origPort, Loc fixed);
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PllCfgRecord get_pll_settings(double f_ref, double f_core, int mode, int low_jitter, bool pdiv0_mux, bool feedback);
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CellInfo *move_ram_i(CellInfo *cell, IdString origPort, bool place = true);
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CellInfo *move_ram_o(CellInfo *cell, IdString origPort, bool place = true);
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CellInfo *move_ram_i_fixed(CellInfo *cell, IdString origPort, Loc fixed);
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CellInfo *move_ram_o_fixed(CellInfo *cell, IdString origPort, Loc fixed);
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CellInfo *move_ram_io(CellInfo *cell, IdString iPort, IdString oPort, bool place = true);
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uint8_t ram_ctrl_signal(CellInfo *cell, IdString port, bool alt);
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uint8_t ram_clk_signal(CellInfo *cell, IdString port);
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bool is_gpio_valid_dff(CellInfo *dff);
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BelId get_bank_cpe(int bank);
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// Cell creating
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CellInfo *create_cell_ptr(IdString type, IdString name);
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void flush_cells();
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void pack_ram_cell(CellInfo &ci, CellInfo *cell, int num, bool is_split);
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pool<IdString> packed_cells;
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std::map<NetInfo *, int> global_signals;
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Context *ctx;
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GateMateImpl *uarch;
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HimbaechelHelpers h;
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};
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NEXTPNR_NAMESPACE_END
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#endif
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