nextpnr/himbaechel/uarch/gatemate
gatecat cd1e403c0d Implement getBelValidityConflict for gatemate
Signed-off-by: gatecat <gatecat@ds0.me>
2025-09-04 17:17:24 +02:00
..
gen gatemate: use CPE bridge (#1538) 2025-09-02 18:00:01 +02:00
tests gatemate: optimizations and cleanups (#1517) 2025-07-17 08:50:24 +02:00
CMakeLists.txt gatemate: add iopath delays (#1537) 2025-08-22 11:07:34 +02:00
bitstream.cc gatemate: use CPE bridge (#1538) 2025-09-02 18:00:01 +02:00
ccf.cc gatemate: Multi die support and primitives model improvement (#1501) 2025-06-18 08:32:57 +02:00
cells.cc gatemate: add IOSEL as separate primitive (#1533) 2025-08-14 12:20:24 +02:00
config.cc gatemate: use CPE bridge (#1538) 2025-09-02 18:00:01 +02:00
config.h gatemate: use CPE bridge (#1538) 2025-09-02 18:00:01 +02:00
constids.inc gatemate: Enable placing RAM halfs (#1544) 2025-09-02 08:03:22 +02:00
delay.cc gatemate: use CPE bridge (#1538) 2025-09-02 18:00:01 +02:00
extra_data.h gatemate: use CPE bridge (#1538) 2025-09-02 18:00:01 +02:00
gatemate.cc Implement getBelValidityConflict for gatemate 2025-09-04 17:17:24 +02:00
gatemate.h Implement getBelValidityConflict for gatemate 2025-09-04 17:17:24 +02:00
gatemate_util.h gatemate: optimizations and cleanups (#1517) 2025-07-17 08:50:24 +02:00
gfx.cc Use improved CPE model (#1503) 2025-07-07 10:14:48 +02:00
gfxids.inc Gatemate FPGA initial support (#1473) 2025-04-22 16:41:01 +02:00
pack.cc gatemate: Enable placing RAM halfs (#1544) 2025-09-02 08:03:22 +02:00
pack.h gatemate: Enable placing RAM halfs (#1544) 2025-09-02 08:03:22 +02:00
pack_bram.cc gatemate: Enable placing RAM halfs (#1544) 2025-09-02 08:03:22 +02:00
pack_clocking.cc gatemate: use CPE bridge (#1538) 2025-09-02 18:00:01 +02:00
pack_cpe.cc gatemate: use CPE bridge (#1538) 2025-09-02 18:00:01 +02:00
pack_io.cc gatemate: use CPE bridge (#1538) 2025-09-02 18:00:01 +02:00
pack_mult.cc gatemate: use CPE bridge (#1538) 2025-09-02 18:00:01 +02:00
pack_serdes.cc gatemate: optimizations and cleanups (#1517) 2025-07-17 08:50:24 +02:00
pll.cc gatemate: fix SER_CLK wiring from CLKIN to PLL (#1523) 2025-07-29 11:26:49 +02:00
route_clock.cc gatemate: use CPE bridge (#1538) 2025-09-02 18:00:01 +02:00
route_mult.cc gatemate: fix fourgroup for multi die (#1550) 2025-09-03 12:20:11 +02:00