mirror of https://github.com/YosysHQ/nextpnr.git
c39f26e93a
pack_lutffs constrains an FF into the same slice position as the LUT driving its D input. When that driver is an SRL or LUTRAM cell it has a CLK of its own: the slice write clock. A slice has a single CLK input per half, so the placement validity check (xc7_logic_tile_valid) rejects any slice where the FF clock and the memory write clock differ in net or polarity. Pairing such an FF anyway creates a relatively-constrained cluster that is invalid at every bel on the device; the placer's strict legalisation phase then spins forever trying to place it (observed as a static-placer hang on a design clocking an SRL and its capture FF from different clocks). Only pair the FF when the driving cell either has no CLK or shares the FF's clock net and IS_CLK_INVERTED polarity. Hardware-verified on xc7a100t as part of a MEGA65 core port that previously hung in placement. Co-Authored-By: Claude Fable 5 <noreply@anthropic.com> |
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| .. | ||
| himbaechel_dbgen | ||
| uarch | ||
| .gitignore | ||
| CMakeLists.txt | ||
| arch.cc | ||
| arch.h | ||
| arch_pybindings.cc | ||
| arch_pybindings.h | ||
| archdefs.h | ||
| chipdb.h | ||
| himbaechel_api.cc | ||
| himbaechel_api.h | ||
| himbaechel_constids.h | ||
| himbaechel_gfxids.h | ||
| himbaechel_helpers.cc | ||
| himbaechel_helpers.h | ||
| main.cc | ||
| test_main.cc | ||