mirror of https://github.com/YosysHQ/nextpnr.git
46fbe7c6d7
* gatemate: clock router Co-authored-by: Miodrag Milanovic <mmicko@gmail.com> * Re-add clock router pip binding * Refactoring * Require globals to use a BUFG * Fix misunderstanding of GPIO/RAM clocking * Add plane info to chipdb * Force clock routing along a specific plane * Remove overly-limiting condition * Move clock router into its own file * Clock router based on delay * Refine clock router conditions * More detailed clock routing output * Clean up debug messages * clangformat --------- Co-authored-by: Miodrag Milanovic <mmicko@gmail.com> |
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