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CMakeLists.txt
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[himbaechel/gowin] Add GW1N-2 device
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2026-06-13 16:59:41 -06:00 |
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constids.inc
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Gowin. Implement GW5A HCLK and CLKDIV2. (#1687)
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2026-04-03 09:40:45 +02:00 |
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cst.cc
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Gowin. Ignore empty lines. (#1626)
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2026-01-20 08:11:48 +01:00 |
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cst.h
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gowin: Himbaechel. Add constraint file processing.
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2023-08-31 08:28:09 +02:00 |
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globals.cc
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Gowin. Add GW5AST-138C chip. (#1631)
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2026-01-31 13:01:22 +01:00 |
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globals.h
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gowin: Himbaechel. Add a clock router.
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2023-08-31 08:28:09 +02:00 |
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gowin.cc
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gowin: Initial estimateDelay and ripup penalty (#1708)
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2026-04-30 08:07:11 +02:00 |
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gowin.h
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Gowin. Implement GW5A HCLK and CLKDIV2. (#1687)
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2026-04-03 09:40:45 +02:00 |
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gowin_arch_gen.py
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Merge 59c8f93a62 into 2fb1d1982f
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2026-08-04 10:33:13 +02:00 |
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gowin_utils.cc
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Gowin. Implement GW5A HCLK and CLKDIV2. (#1687)
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2026-04-03 09:40:45 +02:00 |
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gowin_utils.h
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Gowin. Implement GW5A HCLK and CLKDIV2. (#1687)
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2026-04-03 09:40:45 +02:00 |
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pack.cc
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Gowin. Implement CLKDIV. (#1691)
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2026-04-06 15:34:34 +02:00 |
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pack.h
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gowin: add DL-series latch cell support (#1652)
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2026-03-14 19:12:08 +00:00 |
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pack_bsram.cc
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GOWIN. BUGFIX. BSRAM port renaming. (#1669)
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2026-03-14 20:52:05 +00:00 |
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pack_dsp.cc
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Gowin. DSP. Refactor port renaming.
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2026-03-04 09:04:55 +01:00 |
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pack_io.cc
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Gowin. Divide packer. (#1645)
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2026-02-21 08:11:39 +01:00 |
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pack_iologic.cc
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Gowin. Implement GW5A HCLK and CLKDIV2. (#1687)
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2026-04-03 09:40:45 +02:00 |
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pack_luts.cc
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Gowin. BUGFIX. Alu optimization. (#1736)
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2026-06-17 08:48:25 +02:00 |
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