mirror of https://github.com/YosysHQ/nextpnr.git
a652a752de
pack_bram unconditionally disconnected ADDRARDADDRL15/ADDRBWRADDRL15 on every RAMB36E1 and tied them to VCC. Tying high is correct for non-cascaded modes, but in a depth-cascaded pair (RAM_EXTENSION_A/B = LOWER/UPPER) these pins carry the address MSB that selects between the two 32K halves, and the port multixform has already wired ADDRARDADDR[15] onto them. Overriding that with VCC pinned both reads and writes to the upper half: address bit 15 was simply ignored. Keep the tie as a fallback for undriven pins only. Hardware-verified on xc7a100t: a 128K ROM built from cascaded RAMB36E1 pairs passes a full 32/32 content fingerprint check that failed before this change. Co-Authored-By: Claude Fable 5 <noreply@anthropic.com> |
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| .. | ||
| himbaechel_dbgen | ||
| uarch | ||
| .gitignore | ||
| CMakeLists.txt | ||
| arch.cc | ||
| arch.h | ||
| arch_pybindings.cc | ||
| arch_pybindings.h | ||
| archdefs.h | ||
| chipdb.h | ||
| himbaechel_api.cc | ||
| himbaechel_api.h | ||
| himbaechel_constids.h | ||
| himbaechel_gfxids.h | ||
| himbaechel_helpers.cc | ||
| himbaechel_helpers.h | ||
| main.cc | ||
| test_main.cc | ||