mirror of https://github.com/YosysHQ/nextpnr.git
a18bd2e055
Very rarely (about once a year), the dedicated clock router would malfunction, issuing an incorrect route. The reason turned out to be the so-called gate wires to the global clock wire system from the logic. Among the PIPs for which these wires are sinks, there are PIPs where the sources are also clock wires. This leads to the possibility of feeding the clock signal back into the gate and again into the global clock MUX. If handled carelessly, this can lead to a complete loop. But the loop option itself is particularly useful in the case of DCS (dynamic clock selection) - the fact is that because these primitives have four clock inputs and each of them could theoretically address all 56 clock sources, but in practice there are not enough wires and the DCS inputs cannot serve as sinks for all clock sources. The simplest solution (and the one that currently works) is to use the gate to re-enter the clock system, but this time changing the clock source. This commit explicitly marks wires as gates and removes the possibility of looping (however unlikely it may be) where a loop is not needed. Signed-off-by: YRabbit <rabbit@yrabbit.cyou> |
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| .. | ||
| CMakeLists.txt | ||
| constids.inc | ||
| cst.cc | ||
| cst.h | ||
| globals.cc | ||
| globals.h | ||
| gowin.cc | ||
| gowin.h | ||
| gowin_arch_gen.py | ||
| gowin_utils.cc | ||
| gowin_utils.h | ||
| pack.cc | ||
| pack.h | ||