mirror of https://github.com/YosysHQ/nextpnr.git
c13b34f20e
The following primitives are implemented for the GW1N-1, GW2A-18,
GW2AR-18C, GW1NSR-4C, GW1NR-9C, GW1NR-9 and GW1N-4 chips:
* pROM - read only memory - (bitwidth: 1, 2, 4, 8, 16, 32).
* pROMX9 - read only memory - (bitwidth: 9, 18, 36).
* SDPB - semidual port - (bitwidth: 1, 2, 4, 8, 16, 32).
* SDPX9B - semidual port - (bitwidth: 9, 18, 36).
* DPB - dual port - (bitwidth: 16).
* DPX9B - dual port - (bitwidth: 18).
* SP - single port - (bitwidth: 1, 2, 4, 8, 16, 32).
* SPX9 - single port - (bitwidth: 9, 18, 36).
For GW1NSR-4C and GW1NR-9 chips, SP/SPX9 primitives with data widths
of 32/36 bits are implemented using a pair of 16-bit wide
primitives.
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
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| .. | ||
| CMakeLists.txt | ||
| constids.inc | ||
| cst.cc | ||
| cst.h | ||
| globals.cc | ||
| globals.h | ||
| gowin.cc | ||
| gowin.h | ||
| gowin_arch_gen.py | ||
| gowin_utils.cc | ||
| gowin_utils.h | ||
| pack.cc | ||
| pack.h | ||