mirror of https://github.com/YosysHQ/nextpnr.git
864c1e471d
Gowin chips have an interesting mechanism - wires that run vertically through several rows (at least 10) in each column of the chip. In each row a particular wire has branches to the left and right, covering on average 4 neighboring cells in the row. For lack of a better term, I further call such a wire a segment. So a segment can provide a direct connection in a local rectangle. There are no special restrictions on the sinks, so segment networks can be used for ClockEnable, LocalSetReset, as well as for LUT and DFF inputs. The sources are not so simple - the sources can be the upper or lower end of the segment, which in theory can lead to unfortunate consequences if the signal is applied from both ends. The matter is complicated by the fact that there are default connections, i.e. in the absence of any set fuse the segment input is still connected to something (VCC for example) and to disable the unused end of the segment you need to set a special combination of fuses. Taking into account which end of which segment is used is one of the tasks of this router. In addition, segment ends can physically coincide with PLL, DSP and BSRAM inputs, which can also lead to unexpected effects. Some of these things are tracked when generating the base, some in this router, some when packing in gowin_pack. Signed-off-by: YRabbit <rabbit@yrabbit.cyou> |
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| .. | ||
| CMakeLists.txt | ||
| constids.inc | ||
| cst.cc | ||
| cst.h | ||
| globals.cc | ||
| globals.h | ||
| gowin.cc | ||
| gowin.h | ||
| gowin_arch_gen.py | ||
| gowin_utils.cc | ||
| gowin_utils.h | ||
| pack.cc | ||
| pack.h | ||