mirror of https://github.com/YosysHQ/nextpnr.git
632 lines
25 KiB
C++
632 lines
25 KiB
C++
/*
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* nextpnr -- Next Generation Place and Route
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*
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* Copyright (C) 2024 The Project Peppercorn Authors.
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#include "design_utils.h"
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#include "gatemate_util.h"
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#include "pack.h"
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#define HIMBAECHEL_CONSTIDS "uarch/gatemate/constids.inc"
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#include "himbaechel_constids.h"
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NEXTPNR_NAMESPACE_BEGIN
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// Return true if a cell is a flipflop
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inline bool is_dff(const BaseCtx *ctx, const CellInfo *cell) { return cell->type.in(id_CC_DFF, id_CC_DLT); }
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void GateMatePacker::dff_to_cpe(CellInfo *dff)
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{
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bool invert;
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bool is_latch = dff->type == id_CC_DLT;
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if (is_latch) {
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NetInfo *g_net = dff->getPort(id_G);
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invert = bool_or_default(dff->params, id_G_INV, 0);
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if (g_net) {
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if (g_net->name == ctx->id("$PACKER_GND")) {
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dff->params[id_C_CPE_CLK] = Property(invert ? 0b11 : 0b00, 2);
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dff->disconnectPort(id_G);
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} else if (g_net->name == ctx->id("$PACKER_VCC")) {
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dff->params[id_C_CPE_CLK] = Property(invert ? 0b00 : 0b11, 2);
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dff->disconnectPort(id_G);
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} else {
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dff->params[id_C_CPE_CLK] = Property(invert ? 0b01 : 0b10, 2);
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}
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} else {
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dff->params[id_C_CPE_CLK] = Property(invert ? 0b11 : 0b00, 2);
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}
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dff->unsetParam(id_G_INV);
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dff->renamePort(id_G, id_CLK);
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dff->params[id_C_CPE_EN] = Property(0b11, 2);
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dff->params[id_C_L_D] = Property(0b1, 1);
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} else {
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NetInfo *en_net = dff->getPort(id_EN);
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bool invert = bool_or_default(dff->params, id_EN_INV, 0);
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if (en_net) {
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if (en_net->name == ctx->id("$PACKER_GND")) {
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dff->params[id_C_CPE_EN] = Property(invert ? 0b11 : 0b00, 2);
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dff->disconnectPort(id_EN);
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} else if (en_net->name == ctx->id("$PACKER_VCC")) {
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dff->params[id_C_CPE_EN] = Property(invert ? 0b00 : 0b11, 2);
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dff->disconnectPort(id_EN);
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} else {
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dff->params[id_C_CPE_EN] = Property(invert ? 0b01 : 0b10, 2);
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}
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} else {
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dff->params[id_C_CPE_EN] = Property(invert ? 0b11 : 0b00, 2);
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}
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dff->unsetParam(id_EN_INV);
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NetInfo *clk_net = dff->getPort(id_CLK);
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invert = bool_or_default(dff->params, id_CLK_INV, 0);
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if (clk_net) {
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if (clk_net->name == ctx->id("$PACKER_GND")) {
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dff->params[id_C_CPE_CLK] = Property(invert ? 0b11 : 0b00, 2);
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dff->disconnectPort(id_CLK);
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} else if (clk_net->name == ctx->id("$PACKER_VCC")) {
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dff->params[id_C_CPE_CLK] = Property(invert ? 0b00 : 0b11, 2);
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dff->disconnectPort(id_CLK);
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} else {
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dff->params[id_C_CPE_CLK] = Property(invert ? 0b01 : 0b10, 2);
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}
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} else {
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dff->params[id_C_CPE_CLK] = Property(invert ? 0b11 : 0b00, 2);
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}
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dff->unsetParam(id_CLK_INV);
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}
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NetInfo *sr_net = dff->getPort(id_SR);
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invert = bool_or_default(dff->params, id_SR_INV, 0);
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bool sr_val = bool_or_default(dff->params, id_SR_VAL, 0);
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if (sr_net) {
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if (sr_net->name.in(ctx->id("$PACKER_GND"), ctx->id("$PACKER_VCC"))) {
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bool sr_signal = sr_net->name == ctx->id("$PACKER_VCC");
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if (sr_signal ^ invert) {
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if (sr_val) {
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dff->params[id_C_CPE_RES] = Property(0b11, 2);
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dff->params[id_C_CPE_SET] = Property(0b00, 2);
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} else {
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dff->params[id_C_CPE_RES] = Property(0b00, 2);
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dff->params[id_C_CPE_SET] = Property(0b11, 2);
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}
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} else {
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dff->params[id_C_CPE_RES] = Property(0b11, 2);
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dff->params[id_C_CPE_SET] = Property(0b11, 2);
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}
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dff->disconnectPort(id_SR);
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} else {
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if (sr_val) {
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dff->params[id_C_CPE_RES] = Property(0b11, 2);
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dff->params[id_C_CPE_SET] = Property(invert ? 0b10 : 0b01, 2);
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if (is_latch)
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dff->renamePort(id_SR, id_EN);
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else
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dff->params[id_C_EN_SR] = Property(0b1, 1);
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} else {
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dff->params[id_C_CPE_RES] = Property(invert ? 0b10 : 0b01, 2);
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dff->params[id_C_CPE_SET] = Property(0b11, 2);
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}
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}
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} else {
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dff->params[id_C_CPE_RES] = Property(0b11, 2);
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dff->params[id_C_CPE_SET] = Property(0b11, 2);
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}
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dff->unsetParam(id_SR_VAL);
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dff->unsetParam(id_SR_INV);
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if (dff->params.count(id_INIT) && dff->params[id_INIT].is_fully_def()) {
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bool init = bool_or_default(dff->params, id_INIT, 0);
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if (init)
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dff->params[id_FF_INIT] = Property(0b11, 2);
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else
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dff->params[id_FF_INIT] = Property(0b10, 2);
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dff->unsetParam(id_INIT);
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} else {
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dff->unsetParam(id_INIT);
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}
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}
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void GateMatePacker::pack_cpe()
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{
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log_info("Packing CPEs..\n");
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std::vector<CellInfo *> l2t5_list;
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for (auto &cell : ctx->cells) {
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CellInfo &ci = *cell.second;
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if (!ci.type.in(id_CC_L2T4, id_CC_L2T5, id_CC_LUT2, id_CC_LUT1, id_CC_MX2))
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continue;
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if (ci.type == id_CC_L2T5) {
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l2t5_list.push_back(&ci);
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ci.renamePort(id_I0, id_IN1);
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ci.renamePort(id_I1, id_IN2);
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ci.renamePort(id_I2, id_IN3);
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ci.renamePort(id_I3, id_IN4);
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ci.renamePort(id_O, id_OUT);
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uarch->rename_param(&ci, id_INIT_L02, id_INIT_L00, 4);
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uarch->rename_param(&ci, id_INIT_L03, id_INIT_L01, 4);
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uarch->rename_param(&ci, id_INIT_L11, id_INIT_L10, 4);
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ci.cluster = ci.name;
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ci.constr_abs_z = true;
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ci.constr_z = CPE_LT_L_Z;
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ci.type = id_CPE_L2T4;
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} else if (ci.type == id_CC_MX2) {
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ci.renamePort(id_D1, id_IN1);
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NetInfo *sel = ci.getPort(id_S0);
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ci.renamePort(id_S0, id_IN2);
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ci.ports[id_IN3].name = id_IN3;
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ci.ports[id_IN3].type = PORT_IN;
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ci.connectPort(id_IN3, sel);
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ci.renamePort(id_D0, id_IN4);
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ci.disconnectPort(id_D1);
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ci.params[id_INIT_L00] = Property(0b1000, 4); // AND
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ci.params[id_INIT_L01] = Property(0b0100, 4); // AND inv D0
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ci.params[id_INIT_L10] = Property(0b1110, 4); // OR
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ci.renamePort(id_Y, id_OUT);
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ci.type = id_CPE_L2T4;
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} else {
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ci.renamePort(id_I0, id_IN1);
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ci.renamePort(id_I1, id_IN2);
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ci.renamePort(id_I2, id_IN3);
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ci.renamePort(id_I3, id_IN4);
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ci.renamePort(id_O, id_OUT);
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if (ci.type.in(id_CC_LUT1, id_CC_LUT2)) {
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uint8_t val = int_or_default(ci.params, id_INIT, 0);
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if (ci.type == id_CC_LUT1)
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val = val << 2 | val;
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ci.params[id_INIT_L00] = Property(val, 4);
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ci.unsetParam(id_INIT);
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ci.params[id_INIT_L10] = Property(0b1010, 4);
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}
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ci.type = id_CPE_L2T4;
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}
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NetInfo *o = ci.getPort(id_OUT);
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if (o) {
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CellInfo *dff = net_only_drives(ctx, o, is_dff, id_D, true);
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if (dff) {
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dff->cluster = ci.name;
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dff->constr_abs_z = false;
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dff->constr_z = +2;
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ci.cluster = ci.name;
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ci.constr_children.push_back(dff);
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dff->renamePort(id_D, id_DIN);
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dff->renamePort(id_Q, id_DOUT);
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dff_to_cpe(dff);
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dff->type = (dff->type == id_CC_DLT) ? id_CPE_LATCH : id_CPE_FF;
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}
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}
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}
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for (auto ci : l2t5_list) {
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CellInfo *upper = create_cell_ptr(id_CPE_L2T4, ctx->idf("%s$upper", ci->name.c_str(ctx)));
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upper->cluster = ci->name;
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upper->constr_abs_z = true;
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upper->constr_z = CPE_LT_U_Z;
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ci->movePortTo(id_I4, upper, id_IN1);
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upper->params[id_INIT_L00] = Property(0b1010, 4);
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upper->params[id_INIT_L10] = Property(0b1010, 4);
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ci->constr_children.push_back(upper);
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NetInfo *ci_out_conn = ctx->createNet(ctx->idf("%s$combin", ci->name.c_str(ctx)));
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upper->connectPort(id_OUT, ci_out_conn);
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ci->ports[id_COMBIN].name = id_COMBIN;
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ci->ports[id_COMBIN].type = PORT_IN;
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ci->connectPort(id_COMBIN, ci_out_conn);
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}
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l2t5_list.clear();
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flush_cells();
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std::vector<CellInfo *> mux_list;
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for (auto &cell : ctx->cells) {
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CellInfo &ci = *cell.second;
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if (!ci.type.in(id_CC_MX4))
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continue;
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mux_list.push_back(&ci);
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}
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for (auto &cell : mux_list) {
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CellInfo &ci = *cell;
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ci.cluster = ci.name;
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ci.renamePort(id_Y, id_OUT);
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ci.renamePort(id_S0, id_IN2); // IN6
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ci.renamePort(id_S1, id_IN4); // IN8
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uint8_t select = 0;
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uint8_t invert = 0;
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for (int i = 0; i < 4; i++) {
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NetInfo *net = ci.getPort(ctx->idf("D%d", i));
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if (net) {
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if (net->name.in(ctx->id("$PACKER_GND"), ctx->id("$PACKER_VCC"))) {
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if (net->name == ctx->id("$PACKER_VCC"))
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invert |= 1 << i;
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ci.disconnectPort(ctx->idf("D%d", i));
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} else {
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select |= 1 << i;
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}
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}
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}
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ci.params[id_C_FUNCTION] = Property(C_MX4, 3);
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ci.params[id_INIT_L02] = Property(0b1100, 4); // IN6
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ci.params[id_INIT_L03] = Property(0b1100, 4); // IN8
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ci.params[id_INIT_L11] = Property(invert, 4); // Inversion bits
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// ci.params[id_INIT_L20] = Property(0b1100, 4); // Always D1
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ci.type = id_CPE_LT_L;
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CellInfo *upper = create_cell_ptr(id_CPE_LT_U, ctx->idf("%s$upper", ci.name.c_str(ctx)));
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upper->cluster = ci.name;
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upper->constr_abs_z = false;
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upper->constr_z = -1;
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upper->params[id_INIT_L10] = Property(select, 4); // Selection bits
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upper->params[id_C_FUNCTION] = Property(C_MX4, 3);
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ci.movePortTo(id_D0, upper, id_IN1);
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ci.movePortTo(id_D1, upper, id_IN2);
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ci.movePortTo(id_D2, upper, id_IN3);
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ci.movePortTo(id_D3, upper, id_IN4);
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ci.constr_children.push_back(upper);
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}
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mux_list.clear();
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std::vector<CellInfo *> dff_list;
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for (auto &cell : ctx->cells) {
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CellInfo &ci = *cell.second;
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if (!ci.type.in(id_CC_DFF, id_CC_DLT))
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continue;
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dff_list.push_back(&ci);
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}
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for (auto &cell : dff_list) {
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CellInfo &ci = *cell;
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CellInfo *lt = create_cell_ptr(id_CPE_L2T4, ctx->idf("%s$lt", ci.name.c_str(ctx)));
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lt->cluster = ci.name;
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lt->constr_abs_z = false;
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lt->constr_z = -2;
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ci.cluster = ci.name;
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ci.constr_children.push_back(lt);
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ci.renamePort(id_Q, id_DOUT);
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NetInfo *d_net = ci.getPort(id_D);
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if (d_net->name == ctx->id("$PACKER_GND")) {
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lt->params[id_INIT_L00] = Property(0b0000, 4);
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ci.disconnectPort(id_D);
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} else if (d_net->name == ctx->id("$PACKER_VCC")) {
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lt->params[id_INIT_L00] = Property(0b1111, 4);
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ci.disconnectPort(id_D);
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} else {
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lt->params[id_INIT_L00] = Property(0b1010, 4);
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}
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lt->params[id_INIT_L10] = Property(0b1010, 4);
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ci.movePortTo(id_D, lt, id_IN1);
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dff_to_cpe(&ci);
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ci.type = (ci.type == id_CC_DLT) ? id_CPE_LATCH : id_CPE_FF;
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NetInfo *conn = ctx->createNet(ctx->idf("%s$di", ci.name.c_str(ctx)));
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lt->connectPort(id_OUT, conn);
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ci.ports[id_DIN].name = id_DIN;
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ci.ports[id_DIN].type = PORT_IN;
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ci.connectPort(id_DIN, conn);
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}
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dff_list.clear();
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}
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static bool is_addf_ci(NetInfo *net)
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{
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return net && net->users.entries() == 1 && (*net->users.begin()).cell->type == id_CC_ADDF &&
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(*net->users.begin()).port == id_CI;
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}
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void GateMatePacker::pack_addf()
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{
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log_info("Packing ADDFs..\n");
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std::vector<CellInfo *> root_cys;
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for (auto &cell : ctx->cells) {
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CellInfo *ci = cell.second.get();
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if (ci->type != id_CC_ADDF)
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continue;
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NetInfo *ci_net = ci->getPort(id_CI);
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if (!ci_net || !ci_net->driver.cell ||
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!(ci_net->driver.cell->type == id_CC_ADDF && ci_net->driver.port == id_CO)) {
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root_cys.push_back(ci);
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}
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}
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std::vector<std::vector<CellInfo *>> groups;
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for (auto root : root_cys) {
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std::vector<CellInfo *> group;
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CellInfo *cy = root;
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group.push_back(cy);
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while (true) {
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NetInfo *co_net = cy->getPort(id_CO);
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if (co_net) {
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bool found = false;
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for (auto &usr : co_net->users) {
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if (usr.cell->type == id_CC_ADDF && usr.port == id_CI) {
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if (found)
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log_error("Only one other ADDF can be connected.\n");
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cy = usr.cell;
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group.push_back(cy);
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found = true;
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}
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}
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if (!found)
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break;
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} else
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break;
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}
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groups.push_back(group);
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}
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// Merge two ADDF cells to one CPE when possible
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// use artificial CC_ADDF2 cell for that
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for (size_t i = 0; i < groups.size(); i++) {
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std::vector<CellInfo *> regrouped;
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size_t pos = 0;
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auto &grp = groups.at(i);
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while (pos < grp.size()) {
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bool merged = false;
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CellInfo *cy = grp.at(pos);
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NetInfo *co_net = cy->getPort(id_CO);
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bool last = pos + 1 == grp.size();
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if (!last && is_addf_ci(co_net)) {
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CellInfo *cy2 = grp.at(pos + 1);
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co_net = cy2->getPort(id_CO);
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last = pos + 2 == grp.size();
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if (!co_net || last || is_addf_ci(co_net)) {
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cy2->type = id_CC_ADDF2;
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cy2->disconnectPort(id_CI);
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// Do actual merge of cells
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cy->movePortTo(id_A, cy2, id_A2);
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cy->movePortTo(id_B, cy2, id_B2);
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cy->movePortTo(id_S, cy2, id_S2);
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cy->disconnectPort(id_CO);
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cy->movePortTo(id_CI, cy2, id_CI);
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packed_cells.insert(cy->name);
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regrouped.push_back(cy2);
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merged = true;
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pos++;
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}
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}
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if (!merged)
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regrouped.push_back(cy);
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pos++;
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}
|
|
grp = regrouped;
|
|
}
|
|
flush_cells();
|
|
|
|
for (auto &grp : splitNestedVector(groups)) {
|
|
CellInfo *root = grp.front();
|
|
root->cluster = root->name;
|
|
|
|
CellInfo *ci_upper = create_cell_ptr(id_CPE_DUMMY, ctx->idf("%s$ci_upper", root->name.c_str(ctx)));
|
|
root->constr_children.push_back(ci_upper);
|
|
ci_upper->cluster = root->name;
|
|
ci_upper->constr_abs_z = false;
|
|
ci_upper->constr_z = -1;
|
|
ci_upper->constr_y = -1;
|
|
|
|
CellInfo *ci_lower = create_cell_ptr(id_CPE_L2T4, ctx->idf("%s$ci", root->name.c_str(ctx)));
|
|
root->constr_children.push_back(ci_lower);
|
|
ci_lower->cluster = root->name;
|
|
ci_lower->constr_abs_z = false;
|
|
ci_lower->constr_y = -1;
|
|
ci_lower->params[id_INIT_L00] = Property(0b0000, 4); // zero
|
|
ci_lower->params[id_INIT_L10] = Property(0b1010, 4); // D0
|
|
|
|
CellInfo *ci_cplines = create_cell_ptr(id_CPE_CPLINES, ctx->idf("%s$ci_cplines", root->name.c_str(ctx)));
|
|
ci_cplines->params[id_C_SELY1] = Property(1, 1);
|
|
ci_cplines->params[id_C_CY1_I] = Property(1, 1);
|
|
root->constr_children.push_back(ci_cplines);
|
|
ci_cplines->cluster = root->name;
|
|
ci_cplines->constr_abs_z = true;
|
|
ci_cplines->constr_y = -1;
|
|
ci_cplines->constr_z = CPE_CPLINES_Z;
|
|
NetInfo *ci_out_conn = ctx->createNet(ctx->idf("%s$out", ci_lower->name.c_str(ctx)));
|
|
ci_lower->connectPort(id_OUT, ci_out_conn);
|
|
ci_cplines->connectPort(id_OUT1, ci_out_conn);
|
|
|
|
NetInfo *ci_net = root->getPort(id_CI);
|
|
if (ci_net->name == ctx->id("$PACKER_GND")) {
|
|
ci_lower->params[id_INIT_L00] = Property(0b0000, 4);
|
|
root->disconnectPort(id_CI);
|
|
} else if (ci_net->name == ctx->id("$PACKER_VCC")) {
|
|
ci_lower->params[id_INIT_L00] = Property(0b1111, 4);
|
|
root->disconnectPort(id_CI);
|
|
} else {
|
|
root->movePortTo(id_CI, ci_lower, id_IN1);
|
|
ci_lower->params[id_INIT_L00] = Property(0b1010, 4); // IN5
|
|
}
|
|
|
|
NetInfo *ci_conn = ctx->createNet(ctx->idf("%s$ci_net", root->name.c_str(ctx)));
|
|
ci_cplines->connectPort(id_COUTY1, ci_conn);
|
|
|
|
root->ports[id_CINY1].name = id_CINY1;
|
|
root->ports[id_CINY1].type = PORT_IN;
|
|
root->connectPort(id_CINY1, ci_conn);
|
|
|
|
for (size_t i = 0; i < grp.size(); i++) {
|
|
CellInfo *cy = grp.at(i);
|
|
if (i != 0) {
|
|
cy->cluster = root->name;
|
|
root->constr_children.push_back(cy);
|
|
cy->constr_abs_z = false;
|
|
cy->constr_y = +i;
|
|
cy->renamePort(id_CI, id_CINY1);
|
|
}
|
|
|
|
bool merged = cy->type != id_CC_ADDF;
|
|
if (merged) {
|
|
NetInfo *a_net = cy->getPort(id_A2);
|
|
if (a_net->name == ctx->id("$PACKER_GND")) {
|
|
cy->params[id_INIT_L02] = Property(0b0000, 4);
|
|
cy->disconnectPort(id_A2);
|
|
} else if (a_net->name == ctx->id("$PACKER_VCC")) {
|
|
cy->params[id_INIT_L02] = Property(0b1111, 4);
|
|
cy->disconnectPort(id_A2);
|
|
} else {
|
|
cy->renamePort(id_A2, id_IN1);
|
|
cy->params[id_INIT_L02] = Property(0b1010, 4); // IN1
|
|
}
|
|
NetInfo *b_net = cy->getPort(id_B2);
|
|
if (b_net->name == ctx->id("$PACKER_GND")) {
|
|
cy->params[id_INIT_L03] = Property(0b0000, 4);
|
|
cy->disconnectPort(id_B2);
|
|
} else if (b_net->name == ctx->id("$PACKER_VCC")) {
|
|
cy->params[id_INIT_L03] = Property(0b1111, 4);
|
|
cy->disconnectPort(id_B2);
|
|
} else {
|
|
cy->renamePort(id_B2, id_IN3);
|
|
cy->params[id_INIT_L03] = Property(0b1010, 4); // IN3
|
|
}
|
|
cy->params[id_INIT_L11] = Property(0b0110, 4); // XOR
|
|
cy->renamePort(id_S2, id_OUT);
|
|
} else {
|
|
cy->params[id_INIT_L02] = Property(0b0000, 4); // 0
|
|
cy->params[id_INIT_L03] = Property(0b0000, 4); // 0
|
|
cy->params[id_INIT_L11] = Property(0b0110, 4); // XOR
|
|
cy->params[id_INIT_L20] = Property(0b0110, 4); // XOR
|
|
}
|
|
cy->params[id_C_FUNCTION] = Property(merged ? C_ADDF2 : C_ADDF, 3);
|
|
cy->type = id_CPE_LT_L;
|
|
|
|
CellInfo *upper = create_cell_ptr(id_CPE_LT_U, ctx->idf("%s$upper", cy->name.c_str(ctx)));
|
|
upper->cluster = root->name;
|
|
root->constr_children.push_back(upper);
|
|
upper->constr_abs_z = false;
|
|
upper->constr_y = +i;
|
|
upper->constr_z = -1;
|
|
if (merged) {
|
|
cy->movePortTo(id_S, upper, id_OUT);
|
|
} else {
|
|
cy->renamePort(id_S, id_OUT);
|
|
}
|
|
|
|
NetInfo *a_net = cy->getPort(id_A);
|
|
if (a_net->name == ctx->id("$PACKER_GND")) {
|
|
upper->params[id_INIT_L00] = Property(0b0000, 4);
|
|
cy->disconnectPort(id_A);
|
|
} else if (a_net->name == ctx->id("$PACKER_VCC")) {
|
|
upper->params[id_INIT_L00] = Property(0b1111, 4);
|
|
cy->disconnectPort(id_A);
|
|
} else {
|
|
cy->movePortTo(id_A, upper, id_IN1);
|
|
upper->params[id_INIT_L00] = Property(0b1010, 4); // IN1
|
|
}
|
|
NetInfo *b_net = cy->getPort(id_B);
|
|
if (b_net->name == ctx->id("$PACKER_GND")) {
|
|
upper->params[id_INIT_L01] = Property(0b0000, 4);
|
|
cy->disconnectPort(id_B);
|
|
} else if (b_net->name == ctx->id("$PACKER_VCC")) {
|
|
upper->params[id_INIT_L01] = Property(0b1111, 4);
|
|
cy->disconnectPort(id_B);
|
|
} else {
|
|
cy->movePortTo(id_B, upper, id_IN3);
|
|
upper->params[id_INIT_L01] = Property(0b1010, 4); // IN3
|
|
}
|
|
|
|
upper->params[id_INIT_L10] = Property(0b0110, 4); // XOR
|
|
upper->params[id_C_FUNCTION] = Property(merged ? C_ADDF2 : C_ADDF, 3);
|
|
|
|
if (i == grp.size() - 1) {
|
|
if (!cy->getPort(id_CO))
|
|
break;
|
|
CellInfo *co_upper = create_cell_ptr(id_CPE_DUMMY, ctx->idf("%s$co_upper", cy->name.c_str(ctx)));
|
|
co_upper->cluster = root->name;
|
|
root->constr_children.push_back(co_upper);
|
|
co_upper->constr_abs_z = false;
|
|
co_upper->constr_z = -1;
|
|
co_upper->constr_y = +i + 1;
|
|
CellInfo *co_lower = create_cell_ptr(id_CPE_L2T4, ctx->idf("%s$co", cy->name.c_str(ctx)));
|
|
co_lower->cluster = root->name;
|
|
root->constr_children.push_back(co_lower);
|
|
co_lower->constr_abs_z = false;
|
|
co_lower->constr_y = +i + 1;
|
|
co_lower->params[id_C_FUNCTION] = Property(C_EN_CIN, 3);
|
|
co_lower->params[id_INIT_L10] = Property(0b1100, 4);
|
|
co_lower->params[id_INIT_L20] = Property(0b1100, 4);
|
|
|
|
NetInfo *co_conn = ctx->createNet(ctx->idf("%s$co_net", cy->name.c_str(ctx)));
|
|
|
|
co_lower->connectPort(id_CINY1, co_conn);
|
|
cy->ports[id_COUTY1].name = id_COUTY1;
|
|
cy->ports[id_COUTY1].type = PORT_OUT;
|
|
cy->connectPort(id_COUTY1, co_conn);
|
|
|
|
cy->movePortTo(id_CO, co_lower, id_OUT);
|
|
} else {
|
|
NetInfo *co_net = cy->getPort(id_CO);
|
|
if (!co_net || co_net->users.entries() == 1) {
|
|
cy->renamePort(id_CO, id_COUTY1);
|
|
} else {
|
|
for (auto &usr : co_net->users) {
|
|
if (usr.cell->type == id_CC_ADDF || usr.port == id_CI) {
|
|
usr.cell->disconnectPort(id_CI);
|
|
NetInfo *co_conn = ctx->createNet(ctx->idf("%s$co_net", cy->name.c_str(ctx)));
|
|
cy->ports[id_COUTY1].name = id_COUTY1;
|
|
cy->ports[id_COUTY1].type = PORT_OUT;
|
|
cy->connectPort(id_COUTY1, co_conn);
|
|
usr.cell->connectPort(id_CI, co_conn);
|
|
break;
|
|
}
|
|
}
|
|
cy->movePortTo(id_CO, upper, id_CPOUT);
|
|
}
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
void GateMatePacker::pack_constants()
|
|
{
|
|
log_info("Packing constants..\n");
|
|
// Replace constants with LUTs
|
|
const dict<IdString, Property> vcc_params = {{id_INIT_L10, Property(0b1111, 4)}};
|
|
const dict<IdString, Property> gnd_params = {{id_INIT_L10, Property(0b0000, 4)}};
|
|
|
|
h.replace_constants(CellTypePort(id_CPE_L2T4, id_OUT), CellTypePort(id_CPE_L2T4, id_OUT), vcc_params, gnd_params);
|
|
}
|
|
|
|
void GateMatePacker::remove_constants()
|
|
{
|
|
log_info("Removing constants..\n");
|
|
auto fnd_cell = ctx->cells.find(ctx->id("$PACKER_VCC_DRV"));
|
|
if (fnd_cell != ctx->cells.end()) {
|
|
auto fnd_net = ctx->nets.find(ctx->id("$PACKER_VCC"));
|
|
if (fnd_net != ctx->nets.end() && fnd_net->second->users.entries() == 0) {
|
|
BelId bel = (*fnd_cell).second.get()->bel;
|
|
if (bel != BelId())
|
|
ctx->unbindBel(bel);
|
|
ctx->cells.erase(fnd_cell);
|
|
ctx->nets.erase(fnd_net);
|
|
log_info(" Removed unused VCC cell\n");
|
|
}
|
|
}
|
|
fnd_cell = ctx->cells.find(ctx->id("$PACKER_GND_DRV"));
|
|
if (fnd_cell != ctx->cells.end()) {
|
|
auto fnd_net = ctx->nets.find(ctx->id("$PACKER_GND"));
|
|
if (fnd_net != ctx->nets.end() && fnd_net->second->users.entries() == 0) {
|
|
BelId bel = (*fnd_cell).second.get()->bel;
|
|
if (bel != BelId())
|
|
ctx->unbindBel(bel);
|
|
ctx->cells.erase(fnd_cell);
|
|
ctx->nets.erase(fnd_net);
|
|
log_info(" Removed unused GND cell\n");
|
|
}
|
|
}
|
|
}
|
|
|
|
NEXTPNR_NAMESPACE_END
|