mirror of https://github.com/YosysHQ/nextpnr.git
78ee20b5da
Now the clock router can place a buffer into the specified network, which divides the network into two parts: from the source to the buffer, routing occurs through any available PIPs, and after the buffer to the sink, only through a dedicated global clock network. This is made specifically for the Tangnano20k where the external oscillator is soldered to a regular non-clock pin. But it can be used for other purposes, you just need to remember that the recipient must be a CLK input or output pin. The port/network to set the buffer to is specified in the .CST file: CLOCK_LOC "name" BUFG; Signed-off-by: YRabbit <rabbit@yrabbit.cyou> |
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| .. | ||
| CMakeLists.txt | ||
| constids.inc | ||
| cst.cc | ||
| cst.h | ||
| globals.cc | ||
| globals.h | ||
| gowin.cc | ||
| gowin.h | ||
| gowin_arch_gen.py | ||
| gowin_utils.cc | ||
| gowin_utils.h | ||
| pack.cc | ||
| pack.h | ||