mirror of https://github.com/YosysHQ/nextpnr.git
75c8144d42
A RAMB36E1 port configured with width 1 (true 32K x 1 mode) needs the
RAMB36-level BRAM36_{READ,WRITE}_WIDTH_{A,B}_1 feature in addition to
the per-half RAMB18_Yx width bits, which were the only ones emitted.
In this mode the two 16K halves interleave even/odd bit addresses.
Without the RAMB36-level feature both halves respond at addr>>1:
every write hits the bit pair 2k/2k+1 and the address LSB is ignored,
so half the memory aliases the other half.
Verified against Vivado bitstreams for the same configuration and on
xc7a100t hardware (32K x 1 and cascaded 64K x 1 inferred memories).
Co-Authored-By: Claude Fable 5 <noreply@anthropic.com>
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| .. | ||
| himbaechel_dbgen | ||
| uarch | ||
| .gitignore | ||
| CMakeLists.txt | ||
| arch.cc | ||
| arch.h | ||
| arch_pybindings.cc | ||
| arch_pybindings.h | ||
| archdefs.h | ||
| chipdb.h | ||
| himbaechel_api.cc | ||
| himbaechel_api.h | ||
| himbaechel_constids.h | ||
| himbaechel_gfxids.h | ||
| himbaechel_helpers.cc | ||
| himbaechel_helpers.h | ||
| main.cc | ||
| test_main.cc | ||