mirror of https://github.com/YosysHQ/nextpnr.git
4fd89bca9a
Distributed RAM primitives (RAM32M/RAM64M etc.) carry their per-port initialisation in parameters named INIT_A..INIT_D, but pack_dram looked up INITA..INITD. The lookup never matched, so all LUTRAM was configured with INIT=0 regardless of the design's initial contents. Fixing the name exposed a second, previously unreachable bug in the wide (dbits>1) path: the 64-bit INIT slice was converted with as_bits(), which yields raw bool values rather than the '0'/'1' characters a Property string requires, producing a corrupt property. De-interleave the canonical bit string directly (bit k*2+j of the 64-bit INIT is bit j of entry k) and rebuild the Property with update_intval(). Repro: a RAM32M with a nonzero INIT_A..D readback (WE held low / driven by a live net); before this change the read data is all-zero. Hardware-verified on xc7a100t (QMTech Wukong): LUTRAM-based tables in a MEGA65 core port now read back their initial contents correctly. Co-Authored-By: Claude Fable 5 <noreply@anthropic.com> |
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| .. | ||
| himbaechel_dbgen | ||
| uarch | ||
| .gitignore | ||
| CMakeLists.txt | ||
| arch.cc | ||
| arch.h | ||
| arch_pybindings.cc | ||
| arch_pybindings.h | ||
| archdefs.h | ||
| chipdb.h | ||
| himbaechel_api.cc | ||
| himbaechel_api.h | ||
| himbaechel_constids.h | ||
| himbaechel_gfxids.h | ||
| himbaechel_helpers.cc | ||
| himbaechel_helpers.h | ||
| main.cc | ||
| test_main.cc | ||