mirror of https://github.com/YosysHQ/nextpnr.git
124 lines
4.4 KiB
C++
124 lines
4.4 KiB
C++
/*
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* nextpnr -- Next Generation Place and Route
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*
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* Copyright (C) 2024 The Project Peppercorn Authors.
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#ifndef HIMBAECHEL_GATEMATE_H
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#define HIMBAECHEL_GATEMATE_H
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#include "extra_data.h"
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#include "himbaechel_api.h"
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#include "log.h"
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#include "nextpnr.h"
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#include "util.h"
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#include "himbaechel_helpers.h"
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NEXTPNR_NAMESPACE_BEGIN
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struct GateMateImpl : HimbaechelAPI
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{
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~GateMateImpl();
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void init_database(Arch *arch) override;
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void init(Context *ctx) override;
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void pack() override;
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void prePlace() override;
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void postPlace() override;
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void preRoute() override;
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void postRoute() override;
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BoundingBox getRouteBoundingBox(WireId src, WireId dst) const override;
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void expandBoundingBox(BoundingBox &bb) const override;
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bool isBelLocationValid(BelId bel, bool explain_invalid = false) const override;
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delay_t estimateDelay(WireId src, WireId dst) const override;
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bool getCellDelay(const CellInfo *cell, IdString fromPort, IdString toPort, DelayQuad &delay) const override;
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TimingPortClass getPortTimingClass(const CellInfo *cell, IdString port, int &clockInfoCount) const override;
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TimingClockingInfo getPortClockingInfo(const CellInfo *cell, IdString port, int index) const override;
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void drawBel(std::vector<GraphicElement> &g, GraphicElement::style_t style, IdString bel_type, Loc loc) override;
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bool getClusterPlacement(ClusterId cluster, BelId root_bel,
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std::vector<std::pair<CellInfo *, BelId>> &placement) const override;
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IdString getBelBucketForCellType(IdString cell_type) const override;
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bool isValidBelForCellType(IdString cell_type, BelId bel) const override;
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BelBucketId getBelBucketForBel(BelId bel) const override;
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Loc getRelativeConstraint(Loc &root_loc, IdString id) const;
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void configurePlacerHeap(PlacerHeapCfg &cfg) override;
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bool isPipInverting(PipId pip) const override;
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const GateMateTileExtraDataPOD *tile_extra_data(int tile) const;
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int get_dff_config(CellInfo *dff) const;
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int get_ram_config(CellInfo *ram) const;
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std::set<IdString> available_pads;
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std::map<BelId, const PadInfoPOD *> bel_to_pad;
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pool<IdString> ddr_nets;
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dict<std::pair<IdString, int>, Loc> locations;
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int dies;
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int preferred_die;
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pool<IdString> multiplier_a_passthru_lowers;
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pool<IdString> multiplier_a_passthru_uppers;
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pool<IdString> multiplier_zero_drivers;
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std::vector<CellInfo *> multipliers;
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int fpga_mode;
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int timing_mode;
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private:
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bool getChildPlacement(const BaseClusterInfo *cluster, Loc root_loc,
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std::vector<std::pair<CellInfo *, BelId>> &placement) const;
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void write_bitstream(const std::string &device, const std::string &filename);
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void parse_ccf(const std::string &filename);
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void assign_cell_info();
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void route_clock();
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void route_mult();
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void repack();
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const GateMateBelExtraDataPOD *bel_extra_data(BelId bel) const;
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bool get_delay_from_tmg_db(IdString id, DelayQuad &delay) const;
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void get_setuphold_from_tmg_db(IdString id_setup, IdString id_hold, DelayPair &setup, DelayPair &hold) const;
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void get_setuphold_from_tmg_db(IdString id_setuphold, DelayPair &setup, DelayPair &hold) const;
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struct GateMateCellInfo
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{
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// slice info
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const NetInfo *ff_en = nullptr, *ff_clk = nullptr, *ff_sr = nullptr;
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int config = 0;
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int signal_used = -1;
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bool used = false;
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};
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std::vector<GateMateCellInfo> fast_cell_info;
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std::map<BelId, std::map<IdString, const GateMateBelPinConstraintPOD *>> pin_to_constr;
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std::map<IdString, const GateMateTimingExtraDataPOD *> timing;
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dict<IdString, int> ram_signal_clk;
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};
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NEXTPNR_NAMESPACE_END
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#endif
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