nextpnr/himbaechel/uarch/gowin
YRabbit 1ce187ab5a
Gowin. BUGFIX. BSRAM SP separation. (#1622)
* Gowin. BUGFIX. BSRAM SP separation.

The new SP cell must inherit the byte size - 8 or 9 bits.

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>

* Gowin. Byte Enables processing in SP.

Single Port with a data width of 32/36 is internally configured as Dual
Port with 16/18. Even and odd words are processed separately by ports A
and B.

With the advent of byte enable support, it became necessary to switch
these signals differently.

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>

---------

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
2026-01-05 11:27:43 +01:00
..
CMakeLists.txt Gowin. Enable GW5A series. (#1534) 2025-08-15 07:12:09 +02:00
constids.inc Gowin. Implemenet special ADC IO. (#1598) 2025-11-18 12:44:15 +01:00
cst.cc Gowin. Implemenet special ADC IO. (#1598) 2025-11-18 12:44:15 +01:00
cst.h gowin: Himbaechel. Add constraint file processing. 2023-08-31 08:28:09 +02:00
globals.cc Gowin. GW5A chips. Implement the DCS primitive. (#1558) 2025-09-23 12:42:33 +02:00
globals.h gowin: Himbaechel. Add a clock router. 2023-08-31 08:28:09 +02:00
gowin.cc Gowin. Take the arch arguments directly. (#1592) 2025-10-23 07:58:01 +02:00
gowin.h Gowin. Implemenet special ADC IO. (#1598) 2025-11-18 12:44:15 +01:00
gowin_arch_gen.py Gowin. Implemenet special ADC IO. (#1598) 2025-11-18 12:44:15 +01:00
gowin_utils.cc Gowin. Add BSRAM SDP fix. (#1575) 2025-10-13 11:07:39 +02:00
gowin_utils.h Gowin. Add BSRAM SDP fix. (#1575) 2025-10-13 11:07:39 +02:00
pack.cc Gowin. BUGFIX. BSRAM SP separation. (#1622) 2026-01-05 11:27:43 +01:00
pack.h gowin: Himbaechel. Add ALU. 2023-08-31 08:28:09 +02:00