mirror of https://github.com/YosysHQ/nextpnr.git
2e8280a949
It seems that the internal registers on the BSRAM output pins in READ_MODE=1'b1 (pipeline) mode do not function properly because in the images generated by Gowin IDE an external register is added to each pin, and the BSRAM itself switches to READ_MODE=1'b0 (bypass) mode . This is observed on Tangnano9k and Tangnano20k boards. Here we repeat this fix. Signed-off-by: YRabbit <rabbit@yrabbit.cyou> |
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| .. | ||
| himbaechel_dbgen | ||
| uarch | ||
| .gitignore | ||
| arch.cc | ||
| arch.h | ||
| arch_pybindings.cc | ||
| arch_pybindings.h | ||
| archdefs.h | ||
| chipdb.h | ||
| family.cmake | ||
| himbaechel_api.cc | ||
| himbaechel_api.h | ||
| himbaechel_constids.h | ||
| himbaechel_helpers.cc | ||
| himbaechel_helpers.h | ||
| main.cc | ||