mirror of https://github.com/YosysHQ/nextpnr.git
1c85dee263
CASCADEOUTA/B -> CASCADEINA/B are dedicated wires that only reach the vertically adjacent RAMB36 site in the same column; the router has no general path for them. Without a placement constraint the two cells of a depth-cascaded pair land on arbitrary sites and routing fails. Cluster each cascade pair in pack_bram (analogous to carry chains). Plain relative (x,y,z) constraints cannot express "next RAMB36 up the column": bel z indices are not uniform across BRAM tiles. Instead, precompute a next-RAMB36-in-column map at init and resolve child bels through a getClusterPlacement override. Hardware-verified on xc7a100t: cascaded 64K x 1 memories place, route and function (128K ROM content fingerprint passes). Co-Authored-By: Claude Fable 5 <noreply@anthropic.com> |
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| .. | ||
| himbaechel_dbgen | ||
| uarch | ||
| .gitignore | ||
| CMakeLists.txt | ||
| arch.cc | ||
| arch.h | ||
| arch_pybindings.cc | ||
| arch_pybindings.h | ||
| archdefs.h | ||
| chipdb.h | ||
| himbaechel_api.cc | ||
| himbaechel_api.h | ||
| himbaechel_constids.h | ||
| himbaechel_gfxids.h | ||
| himbaechel_helpers.cc | ||
| himbaechel_helpers.h | ||
| main.cc | ||
| test_main.cc | ||