mirror of https://github.com/YosysHQ/nextpnr.git
c84879e4d5
DLLDLY is the clock delay primitive that adjust the input clock according to the DLLSTEP signal and outputs the delayed clock. These primitives are associated with clock pins and are "tapped" between the output of this IBUF and the clock networks, leaving the possibility to connect to the original unshifted signal as well, although the latter is not very practical because it is no longer possible to use fast wires. Signed-off-by: YRabbit <rabbit@yrabbit.cyou> |
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| .. | ||
| himbaechel_dbgen | ||
| uarch | ||
| .gitignore | ||
| CMakeLists.txt | ||
| arch.cc | ||
| arch.h | ||
| arch_pybindings.cc | ||
| arch_pybindings.h | ||
| archdefs.h | ||
| chipdb.h | ||
| himbaechel_api.cc | ||
| himbaechel_api.h | ||
| himbaechel_constids.h | ||
| himbaechel_gfxids.h | ||
| himbaechel_helpers.cc | ||
| himbaechel_helpers.h | ||
| main.cc | ||