nextpnr/himbaechel/uarch/gowin
YRabbit 175787b2f0
Gowin. BUGFIX. Alu optimization. (#1736)
Adding freeing of the addition/subtraction mode switch PIP.

We're limiting optimization to just one constant input—cases with two
constant inputs are rare, and this raises questions about how such ALUs
are generated in synthesis.

LUT knowledge calculations have been replaced with table
constants—faster and easier to verify.

Addresses https://github.com/YosysHQ/apicula/issues/514

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
2026-06-17 08:48:25 +02:00
..
CMakeLists.txt Gowin. Divide packer. (#1645) 2026-02-21 08:11:39 +01:00
constids.inc Gowin. Implement GW5A HCLK and CLKDIV2. (#1687) 2026-04-03 09:40:45 +02:00
cst.cc Gowin. Ignore empty lines. (#1626) 2026-01-20 08:11:48 +01:00
cst.h gowin: Himbaechel. Add constraint file processing. 2023-08-31 08:28:09 +02:00
globals.cc Gowin. Add GW5AST-138C chip. (#1631) 2026-01-31 13:01:22 +01:00
globals.h gowin: Himbaechel. Add a clock router. 2023-08-31 08:28:09 +02:00
gowin.cc gowin: Initial estimateDelay and ripup penalty (#1708) 2026-04-30 08:07:11 +02:00
gowin.h Gowin. Implement GW5A HCLK and CLKDIV2. (#1687) 2026-04-03 09:40:45 +02:00
gowin_arch_gen.py Gowin. Implement CLKDIV. (#1691) 2026-04-06 15:34:34 +02:00
gowin_utils.cc Gowin. Implement GW5A HCLK and CLKDIV2. (#1687) 2026-04-03 09:40:45 +02:00
gowin_utils.h Gowin. Implement GW5A HCLK and CLKDIV2. (#1687) 2026-04-03 09:40:45 +02:00
pack.cc Gowin. Implement CLKDIV. (#1691) 2026-04-06 15:34:34 +02:00
pack.h gowin: add DL-series latch cell support (#1652) 2026-03-14 19:12:08 +00:00
pack_bsram.cc GOWIN. BUGFIX. BSRAM port renaming. (#1669) 2026-03-14 20:52:05 +00:00
pack_dsp.cc Gowin. DSP. Refactor port renaming. 2026-03-04 09:04:55 +01:00
pack_io.cc Gowin. Divide packer. (#1645) 2026-02-21 08:11:39 +01:00
pack_iologic.cc Gowin. Implement GW5A HCLK and CLKDIV2. (#1687) 2026-04-03 09:40:45 +02:00
pack_luts.cc Gowin. BUGFIX. Alu optimization. (#1736) 2026-06-17 08:48:25 +02:00