nextpnr/fpga_interchange/examples/tests/counter/run_xilinx.tcl

16 lines
287 B
Tcl

yosys -import
read_verilog $::env(SOURCES)
synth_xilinx -nolutram -nowidelut -nosrl -nodsp
techmap -map $::env(TECHMAP)
# opt_expr -undriven makes sure all nets are driven, if only by the $undef
# net.
opt_expr -undriven
opt_clean
setundef -zero -params
write_json $::env(OUT_JSON)