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nextpnr-0.1

nextpnr-0.2

nextpnr-0.3

nextpnr-0.4

nextpnr-0.5

nextpnr-0.6

nextpnr-0.7

nextpnr-0.8

nextpnr-0.9

f2c736ef81 Beginnings of the multiplier router Hannah Ravensloft 2025-07-13 23:24:20 +0100
6033e84eef fix some output formatting Miodrag Milanovic 2025-07-29 10:06:13 +0200
8a9314cf8e gatemate: fix SER_CLK wiring from CLKIN to PLL Patrick Urban 2025-07-29 10:02:23 +0200
af6e9aa6a3 gatemate: Proper KEEPER handling Miodrag Milanovic 2025-07-28 12:11:32 +0200
2c20ca917c clangformat Miodrag Milanovic 2025-07-28 12:11:07 +0200
356278d068

Gowin. Preparing to support the 5A series. (#1520) YRabbit 2025-07-23 16:45:24 +1000
50cd305d48 Gowin. Recognize GW5A family chips. YRabbit 2025-07-23 08:40:42 +1000
52d2e805db Gowin. Preparing to support the 5A series. YRabbit 2025-07-22 11:02:45 +1000
2d7d1e2408

gatemate: optimizations and cleanups (#1517) Miodrag Milanović 2025-07-17 09:50:24 +0300
715f13db51 review fixes Lofty 2025-07-15 06:14:09 +0100
4831e50843

Gowin. Allow clock network routing from GP pins. (#1518) YRabbit 2025-07-13 17:24:40 +1000
0db35f0776 Gowin. Allow clock network routing from GP pins. YRabbit 2025-07-12 15:39:25 +1000
669901ef75 Add logs for packing sections Miodrag Milanovic 2025-07-11 14:26:45 +0200
349a18521c Keep statistics out for now Miodrag Milanovic 2025-07-11 11:02:48 +0200
36c38c5fa6 Cleanup Miodrag Milanovic 2025-07-10 15:51:20 +0200
840354a28a

Fixes for I3C pins and RPLL (#1516) via 2025-07-10 08:47:49 -0400
3244b09e2c Merge FFs where possible Miodrag Milanovic 2025-07-10 14:15:55 +0200
e630a8033e Fixes for I3C pins and RPLL Matthew Via 2025-07-08 18:50:49 -0400
f786686d50 Add warning for carry chain split Miodrag Milanovic 2025-07-10 12:28:04 +0200
6b8d175ff5 Use special nets for VCC/GND to skip using name Miodrag Milanovic 2025-07-10 10:18:08 +0200
c2aba8eecf Add statistics Miodrag Milanovic 2025-07-10 08:15:29 +0200
24b33c0450 Optimize MX2/4 Miodrag Milanovic 2025-07-09 17:35:36 +0200
048c24eaea Add reporting of optimized cells Miodrag Milanovic 2025-07-09 14:11:50 +0200
d1c8453a1b Optimize DFF/Latch Miodrag Milanovic 2025-07-09 12:01:41 +0200
16c94acda9 Check if DFFs are compatible before merging Miodrag Milanovic 2025-07-09 09:23:32 +0200
cd1217efdb Update FF params and ports first Miodrag Milanovic 2025-07-09 09:03:56 +0200
ffe74b1629 Merge DFF in ADDF Miodrag Milanovic 2025-07-08 14:39:13 +0200
ed356d64af Note actual CPE ports Miodrag Milanovic 2025-07-08 14:09:45 +0200
c83ea0bf9b Merge LUT1/2 to ADDF inputs Miodrag Milanovic 2025-07-08 14:00:04 +0200
6715329a1d Move ramio code to pack_cpe Miodrag Milanovic 2025-07-08 10:06:04 +0200
f8aab41b8b Move repack code Miodrag Milanovic 2025-07-08 09:59:58 +0200
bf0fa39ba9 Merge DFF in MX4 Miodrag Milanovic 2025-07-08 09:29:07 +0200
528f3850a9 Use init enumerations Miodrag Milanovic 2025-07-08 09:07:47 +0200
24785a3219

ecp5: Fix placement of ECLKSYNCB driving PLL CLKFB (#1512) myrtle 2025-07-08 08:50:12 +0200
2a7a1a142f Optimize CC_LUT2 as well Miodrag Milanovic 2025-07-07 16:57:20 +0200
c8d2b1697b Update tests Miodrag Milanovic 2025-07-07 16:33:11 +0200
da6837659f Optimize CC_LUT1 Miodrag Milanovic 2025-07-07 16:33:00 +0200
0b8433e655 Add log output Miodrag Milanovic 2025-07-07 16:23:37 +0200
0ebd7afab9 clangformat Miodrag Milanovic 2025-07-07 10:15:50 +0200
84d8e1abe7

Use improved CPE model (#1503) Miodrag Milanović 2025-07-07 10:14:48 +0200
54f5958ab6 Disable multiplier usage for now Miodrag Milanovic 2025-07-07 09:57:24 +0200
1e76af0567 Cleanups Miodrag Milanovic 2025-07-07 09:37:08 +0200
054a652d4b clangformat Miodrag Milanovic 2025-07-07 08:24:05 +0200
37cb2eda0f Cover cases that could be optimized out Miodrag Milanovic 2025-07-06 16:42:32 +0200
901b30240e do not use cplines so we can merge in one cell Miodrag Milanovic 2025-07-04 12:55:32 +0200
cfa64bf6ca Fix one more place Miodrag Milanovic 2025-07-04 12:17:54 +0200
970c0ec04d Only set some C_I signals when used Miodrag Milanovic 2025-07-04 12:04:43 +0200
04ac025734 look at C_I when doing inversion Miodrag Milanovic 2025-07-04 11:09:33 +0200
6c785e16d6 Fix QVariant deprecation warnings OpenProgger 2025-07-03 17:58:40 +0200
c1a6898f77 Port GUI to Qt6 OpenProgger 2025-07-03 15:50:48 +0200
e340c8e5e8 fix some issues with multfab and f_route Lofty 2025-07-03 14:15:05 +0100
6ff932c4de clangformat Miodrag Milanovic 2025-07-03 14:56:40 +0200
ef23109cbc Updates for ADDCIN Miodrag Milanovic 2025-07-03 14:19:52 +0200
7e39bda445 Update L2T4 model Miodrag Milanovic 2025-07-03 14:15:27 +0200
2d4042d3d5 fix carry gen CINX Lofty 2025-07-03 11:29:16 +0100
44ee7d4e86 connect CINY1 for CarryGenCell Lofty 2025-07-03 11:11:45 +0100
42118f30f1 Handle C_I params Miodrag Milanovic 2025-07-03 12:10:06 +0200
7d4d1b4b9c Connect CPOUTs Miodrag Milanovic 2025-07-03 11:57:23 +0200
77396c7597 Commented line Miodrag Milanovic 2025-07-03 11:34:36 +0200
867402732e connect multfab to its lines Lofty 2025-07-03 10:39:25 +0100
9a68c6b13d fixup, oops Lofty 2025-07-03 10:28:46 +0100
3436c35ae1 fix cite for FRoutingCell Lofty 2025-07-03 10:26:14 +0100
2d7428546d connect f_route to its lines Lofty 2025-07-03 10:20:54 +0100
8fea0ad250 C_EN_CIN fixes Miodrag Milanovic 2025-07-03 11:14:36 +0200
55a3faee72 handing of C_EN_IN Miodrag Milanovic 2025-07-03 11:06:18 +0200
9d9f035c23 Bit of cleanup Miodrag Milanovic 2025-07-03 10:24:53 +0200
c0663d368d wire up a bunch of intermediate signals Lofty 2025-07-02 21:49:30 +0100
643ffd1ccd Clean up B passthrough connections Lofty 2025-07-02 18:11:37 +0100
1f64012c5c clangformat Miodrag Milanovic 2025-07-02 18:15:11 +0200
2b81f8d993 clangformat Miodrag Milanovic 2025-07-02 18:14:49 +0200
27395c73e7 Added comp out connections Miodrag Milanovic 2025-07-02 18:14:35 +0200
37f4e39ab5 Add parts Miodrag Milanovic 2025-07-02 16:19:29 +0200
1c9c7ff39e Added cplines to bpassthru and fixed constant driver for A Miodrag Milanovic 2025-07-02 15:57:16 +0200
625749fa67 ecp5: Improve PLL placement algorithm slightly gatecat 2025-07-02 15:35:39 +0200
1d4b0eeac4

himbaechel: xilinx: misc `CMakeLists.txt` improvements (#1509) José Miguel Sánchez García 2025-07-02 14:58:09 +0200
c80b413277 Make it more as in PR #1513 Miodrag Milanovic 2025-07-01 19:40:04 +0200
25cbe7bfd5 Refactor A connection code Lofty 2025-07-01 13:58:26 +0100
a2bdf5ea2b Cleanup Miodrag Milanovic 2025-07-01 14:48:00 +0200
5c316c5a14 Clean up MsbRoutingCell Lofty 2025-07-01 11:48:48 +0100
4cefb7ea87 Cleanup for adders Miodrag Milanovic 2025-07-01 13:09:42 +0200
b6c7f56a83 Update a passthru to use new primitives Miodrag Milanovic 2025-07-01 12:35:01 +0200
998e3e1e6f Clean up CarryGenCell config Lofty 2025-07-01 11:06:28 +0100
eba75f51fd Remove A passthrough inversion option Lofty 2025-07-01 10:05:25 +0100
88af4b4650 typo fix Miodrag Milanovic 2025-06-30 18:09:43 +0200
5a9be3880a Bounded cell type in gui Miodrag Milanovic 2025-06-30 17:22:29 +0200
9ea60d1c8f Simplify zero Miodrag Milanovic 2025-06-30 16:32:08 +0200
6dc5d8c98a Make sure we at least generate bitstream with all info Miodrag Milanovic 2025-06-30 14:29:03 +0200
1404954a26 Fixe net name to be unique Miodrag Milanovic 2025-06-30 14:00:39 +0200
2215181a46 Revert "remove _lower from name" Miodrag Milanovic 2025-06-30 13:30:08 +0200
69b06ed907 refactor multiplier checking Lofty 2025-06-30 12:26:51 +0100
be652a481d remove _lower from name Miodrag Milanovic 2025-06-30 12:51:51 +0200
4e9ed0c797 Rename some of bels Miodrag Milanovic 2025-06-30 12:38:34 +0200
48a5b87c92 comment the relevant CPE inputs in check_multipliers Lofty 2025-06-30 11:33:44 +0100
662c4bf897 explicitly zero some params in B passthrough Lofty 2025-06-30 11:07:51 +0100
afad9c8cef multiplier support from lofty/gatemate-mult Lofty 2025-06-30 10:43:09 +0100
7ca6fc5ba9 Fixed warning Miodrag Milanovic 2025-06-30 11:28:18 +0200
93d5509350 Add more timings models, need updated values Miodrag Milanovic 2025-06-30 11:10:31 +0200
dcecc3be54 Make CPE_LATCH separate Miodrag Milanovic 2025-06-30 09:44:16 +0200
0e76ff312c Fix signal routing Miodrag Milanovic 2025-06-30 08:38:26 +0200
ee2a5781d8 Resolve name conflicts Miodrag Milanovic 2025-06-29 10:15:35 +0200