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nextpnr-0.1

nextpnr-0.2

nextpnr-0.3

nextpnr-0.4

nextpnr-0.5

nextpnr-0.6

nextpnr-0.7

nextpnr-0.8

nextpnr-0.9

b119041585 another multiplier fix Lofty 2025-09-15 10:43:19 +0100
20cf497e15 another multiplier fix Lofty 2025-09-15 10:37:05 +0100
50a18611ef another multiplier fix Lofty 2025-09-15 10:32:37 +0100
500840ae6b another multiplier fix Lofty 2025-09-15 10:18:30 +0100
50299469fc another multiplier fix Lofty 2025-09-15 09:48:22 +0100
e2d882b056 another multiplier fix Lofty 2025-09-15 09:31:36 +0100
9a1c25d83b another multiplier fix Lofty 2025-09-15 09:21:19 +0100
59285f3332 another multiplier fix Lofty 2025-09-15 09:13:04 +0100
2583f01e29 another multiplier fix Lofty 2025-09-15 09:05:52 +0100
14030606a8 another multiplier fix Lofty 2025-09-15 09:00:17 +0100
bc52b33f94 another multiplier fix Lofty 2025-09-15 08:46:25 +0100
b4ef4cace9 another mult fix Lofty 2025-09-12 17:26:20 +0100
1ba1829a8f more multiplier fixes Lofty 2025-09-12 16:47:45 +0100
0412ef7144 proper parameter check Miodrag Milanovic 2025-09-12 15:30:26 +0200
00cf81e463

gatemate: fix static and handle dynamic FIFO almost full/empty offsets (#1555) Patrick Urban 2025-09-12 15:02:28 +0200
485def603a optimize Miodrag Milanovic 2025-09-12 14:14:57 +0200
84095955d0 gatemate/pack_bram: handle dynamic almost full/empty offsets Patrick Urban 2025-09-12 13:55:37 +0200
c66e422dd0 Do not use actual pip delay, determine best by number of passed pips Miodrag Milanovic 2025-09-12 13:39:37 +0200
48cb371d27 fix clock routing Miodrag Milanovic 2025-09-12 10:54:46 +0200
2823ea385a add PLL delays Miodrag Milanovic 2025-09-12 10:52:54 +0200
f24630c02b tried fixing clock router Miodrag Milanovic 2025-09-11 18:48:50 +0200
10765f7516 cleanup Miodrag Milanovic 2025-09-11 15:20:46 +0200
65d47d0183 add pip delays Miodrag Milanovic 2025-09-11 13:17:52 +0200
30ebf540c3 do not need node delay Miodrag Milanovic 2025-09-11 11:28:26 +0200
ce0a37f666 a few multiplier router fixes Lofty 2025-09-11 15:54:02 +0100
09db7c3fb7 gatemate/pack_bram: fifo read/write pointers are 16 bit wide Patrick Urban 2025-09-11 16:44:30 +0200
9c107213cd gatemate/pack_bram: fix CC_FIFO_40K almost full/empty parameters Patrick Urban 2025-09-11 14:20:11 +0200
72960a052e add plane info for node pips Miodrag Milanovic 2025-09-11 11:07:48 +0200
f669ed54e6 convert nodes to pips Miodrag Milanovic 2025-09-11 10:35:13 +0200
33a91cb196 improved estimateDelay formula lofty/gatemate-estimatedelay2 Lofty 2025-09-10 13:53:47 +0100
b8d2372019 gatemate: BUFG must be optional Miodrag Milanovic 2025-09-10 14:42:47 +0200
8ac7ed161a

gatemate: code cleanup and netlist fix (#1554) Miodrag Milanović 2025-09-10 14:04:42 +0200
5263f8c437 gatemate: code cleanup and netlist fix Miodrag Milanovic 2025-09-10 13:51:23 +0200
f4f031bf16 disable diagonal pips (with r2 debug code) lut_perm Lofty 2025-09-09 12:14:22 +0100
8d99682f5e updated check Miodrag Milanovic 2025-09-08 19:10:17 +0200
0c19b43501 do not use diagonal pips Miodrag Milanovic 2025-09-08 18:14:09 +0200
0b9d7d7be2 gatemate: lut permutation arch changes Miodrag Milanovic 2025-09-08 17:24:31 +0200
9715a1d565

heap: Allow chains to ripup other chains (opt-in only) (#1552) nextpnr-0.9 myrtle 2025-09-05 09:02:19 +0200
141abe60a6

gatemate: cleanup BRAM handling (#1551) Miodrag Milanović 2025-09-05 08:37:29 +0200
2f65614f48 heap: Allow chains to ripup other chains (opt-in only) gatecat 2025-09-04 18:20:44 +0200
cd1e403c0d Implement getBelValidityConflict for gatemate gatecat/place-confl-api-update gatecat 2025-09-04 17:17:24 +0200
9c6b106195 archapi: Add new getBelValidityConflict API gatecat 2025-09-04 16:59:36 +0200
30ca3e073c archapi: Remove never-properly-used getConflictingBelCell API gatecat 2025-09-04 16:51:03 +0200
78a369f0c4 gatemate: cleanup BRAM handling Miodrag Milanovic 2025-09-04 15:56:22 +0200
21bfda4165

gatemate: fix fourgroup for multi die (#1550) Miodrag Milanović 2025-09-03 12:20:11 +0200
3a6ba439c8 gatemate: fix fourgroup for multi die Miodrag Milanovic 2025-09-03 11:59:50 +0200
f238e2c4a5

okami: remove (#1549) Lofty 2025-09-02 18:42:07 +0100
3eb682bcbb

gatemate: use CPE bridge (#1538) Miodrag Milanović 2025-09-02 18:00:01 +0200
8063541665 okami: remove Lofty 2025-09-02 16:55:06 +0100
4b0a3779fb Addressed last one Miodrag Milanovic 2025-09-02 17:22:35 +0200
b178430cd7 adressing review comments Miodrag Milanovic 2025-09-02 17:06:59 +0200
ade5e11883 bump chipdb Miodrag Milanovic 2025-09-02 14:05:03 +0200
7f3eacf8c3 use tile instead of getting name out of bel/pip Miodrag Milanovic 2025-09-02 14:02:25 +0200
c88b9fa0f8 put back to error Miodrag Milanovic 2025-09-02 13:55:12 +0200
ffbcc4418e clangformat Miodrag Milanovic 2025-09-02 13:54:09 +0200
f0e253228f fix Miodrag Milanovic 2025-09-02 13:46:07 +0200
00fc093d70 add debugging Miodrag Milanovic 2025-09-02 13:25:48 +0200
8ead86a3f0 clean up wire binding Lofty 2025-09-02 12:38:28 +0100
0217a2e4df remove #if Lofty 2025-09-02 12:22:13 +0100
8108107800 one wire may feed multiple ports Lofty 2025-09-02 12:18:40 +0100
51cec70501 make sure that the pip used is the one assigned Lofty 2025-09-02 11:39:08 +0100
c064d20f25 use same logic for detecting bridge pips Lofty 2025-09-02 10:39:09 +0100
b443ced7cd Remove need for notifyPipChange Miodrag Milanovic 2025-09-02 09:11:27 +0200
041253f70d debug message Miodrag Milanovic 2025-09-01 18:52:42 +0200
9c60256668 one to be removed after testing Miodrag Milanovic 2025-09-01 15:36:53 +0200
098c915e48 sort data in output for easier compare Miodrag Milanovic 2025-09-01 15:35:21 +0200
9315842403 handle inversion bits Miodrag Milanovic 2025-09-01 13:53:31 +0200
9ce05f4272 reconnect cell ports to new nets Lofty 2025-09-01 11:09:14 +0100
2a2da020d8 recursively reassign bridges Lofty 2025-09-01 10:07:46 +0100
bcdb0b6dac Convert bridge pips into bels Lofty 2025-08-26 13:23:11 +0100
619b13a8b2 delay for CPE_BRIDGE Miodrag Milanovic 2025-08-26 12:47:21 +0200
738ea72f73 Fixed and documented Miodrag Milanovic 2025-08-19 20:03:47 +0200
6598acdfe5 do not use CPE_MULT for MUX routing Miodrag Milanovic 2025-08-19 18:07:37 +0200
5a17ee7752 Use bridge only if CPE is unused Miodrag Milanovic 2025-08-19 14:37:55 +0200
3058b0c2fd Add bridge support Miodrag Milanovic 2025-08-19 09:08:26 +0200
4e4f4ab113

gatemate: update bounding box (#1548) Miodrag Milanović 2025-09-02 14:04:28 +0200
0399b8865e

gatemate: Enable placing RAM halfs (#1544) Miodrag Milanović 2025-09-02 08:03:22 +0200
a18bd2e055

Gowin. BUGFIX. Add data about gate wires. (#1547) YRabbit 2025-09-02 15:51:08 +1000
cf52a10246 Gowin. BUGFIX. Add data about gate wires. YRabbit 2025-09-02 14:19:12 +1000
7d2caf6939 Gowin. Fix style. YRabbit 2025-09-02 01:02:20 +1000
75aa8d16ac Gowin. Implement on-chip oscillator. YRabbit 2025-08-31 10:37:58 +1000
70682cba9a Gowin. Fix style. YRabbit 2025-09-02 01:02:20 +1000
37c8bddb30 cleanup Miodrag Milanovic 2025-09-01 10:17:05 +0200
083d1872ec Gowin. Implement on-chip oscillator. YRabbit 2025-08-31 10:37:58 +1000
0cbf400f7c Fix conflict check Miodrag Milanovic 2025-08-30 20:03:17 +0200
2af5568e98 Fix KEEPER setting Miodrag Milanovic 2025-08-29 19:47:23 +0200
bc086c012f

Gowin. Optimize ALU wiring (#1543) YRabbit 2025-08-30 00:58:26 +1000
878ca1a75c bump chip database version Miodrag Milanovic 2025-08-29 14:58:22 +0200
2cf4572b26 rewire global clocks Miodrag Milanovic 2025-08-29 14:15:05 +0200
0420d39b33 attach ECC pins Miodrag Milanovic 2025-08-29 12:47:57 +0200
b6287fed67 fix cluster setting for cascade mode Miodrag Milanovic 2025-08-29 12:41:58 +0200
42924dec69 Name RAM cells Miodrag Milanovic 2025-08-29 12:30:33 +0200
f25088bdd1 optmize remapping halfs Miodrag Milanovic 2025-08-29 12:22:25 +0200
93c15da8fa move code arround Miodrag Milanovic 2025-08-29 09:22:13 +0200
b452e0e12a Cleanups Miodrag Milanovic 2025-08-29 09:00:42 +0200
8c770dbfb0 Gowin. Fix the style. YRabbit 2025-08-29 00:10:16 +1000
17ca049efd gatemate: Split BRAMs into halfs Miodrag Milanovic 2025-08-28 15:11:21 +0200
224331a2ec Gowin. Optimize ALU wiring YRabbit 2025-08-28 17:15:17 +1000
e1ba78094f gatemate: clean data bitmask Miodrag Milanovic 2025-08-27 12:28:58 +0200
8ab9301dc4 clangformat Miodrag Milanovic 2025-08-27 10:37:39 +0200