nextpnr

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nextpnr-0.1

nextpnr-0.2

nextpnr-0.3

nextpnr-0.4

nextpnr-0.5

nextpnr-0.6

nextpnr-0.7

nextpnr-0.8

nextpnr-0.9

ffbcc4418e clangformat Miodrag Milanovic 2025-09-02 13:54:09 +0200
f0e253228f fix Miodrag Milanovic 2025-09-02 13:46:07 +0200
00fc093d70 add debugging Miodrag Milanovic 2025-09-02 13:25:48 +0200
8ead86a3f0 clean up wire binding Lofty 2025-09-02 12:38:28 +0100
0217a2e4df remove #if Lofty 2025-09-02 12:22:13 +0100
8108107800 one wire may feed multiple ports Lofty 2025-09-02 12:18:40 +0100
51cec70501 make sure that the pip used is the one assigned Lofty 2025-09-02 11:39:08 +0100
c064d20f25 use same logic for detecting bridge pips Lofty 2025-09-02 10:39:09 +0100
b443ced7cd Remove need for notifyPipChange Miodrag Milanovic 2025-09-02 09:11:27 +0200
041253f70d debug message Miodrag Milanovic 2025-09-01 18:52:42 +0200
9c60256668 one to be removed after testing Miodrag Milanovic 2025-09-01 15:36:53 +0200
098c915e48 sort data in output for easier compare Miodrag Milanovic 2025-09-01 15:35:21 +0200
9315842403 handle inversion bits Miodrag Milanovic 2025-09-01 13:53:31 +0200
9ce05f4272 reconnect cell ports to new nets Lofty 2025-09-01 11:09:14 +0100
2a2da020d8 recursively reassign bridges Lofty 2025-09-01 10:07:46 +0100
bcdb0b6dac Convert bridge pips into bels Lofty 2025-08-26 13:23:11 +0100
619b13a8b2 delay for CPE_BRIDGE Miodrag Milanovic 2025-08-26 12:47:21 +0200
738ea72f73 Fixed and documented Miodrag Milanovic 2025-08-19 20:03:47 +0200
6598acdfe5 do not use CPE_MULT for MUX routing Miodrag Milanovic 2025-08-19 18:07:37 +0200
5a17ee7752 Use bridge only if CPE is unused Miodrag Milanovic 2025-08-19 14:37:55 +0200
3058b0c2fd Add bridge support Miodrag Milanovic 2025-08-19 09:08:26 +0200
4e4f4ab113

gatemate: update bounding box (#1548) Miodrag Milanović 2025-09-02 14:04:28 +0200
0399b8865e

gatemate: Enable placing RAM halfs (#1544) Miodrag Milanović 2025-09-02 08:03:22 +0200
a18bd2e055

Gowin. BUGFIX. Add data about gate wires. (#1547) YRabbit 2025-09-02 15:51:08 +1000
cf52a10246 Gowin. BUGFIX. Add data about gate wires. YRabbit 2025-09-02 14:19:12 +1000
7d2caf6939 Gowin. Fix style. YRabbit 2025-09-02 01:02:20 +1000
75aa8d16ac Gowin. Implement on-chip oscillator. YRabbit 2025-08-31 10:37:58 +1000
70682cba9a Gowin. Fix style. YRabbit 2025-09-02 01:02:20 +1000
37c8bddb30 cleanup Miodrag Milanovic 2025-09-01 10:17:05 +0200
083d1872ec Gowin. Implement on-chip oscillator. YRabbit 2025-08-31 10:37:58 +1000
0cbf400f7c Fix conflict check Miodrag Milanovic 2025-08-30 20:03:17 +0200
2af5568e98 Fix KEEPER setting Miodrag Milanovic 2025-08-29 19:47:23 +0200
bc086c012f

Gowin. Optimize ALU wiring (#1543) YRabbit 2025-08-30 00:58:26 +1000
878ca1a75c bump chip database version Miodrag Milanovic 2025-08-29 14:58:22 +0200
2cf4572b26 rewire global clocks Miodrag Milanovic 2025-08-29 14:15:05 +0200
0420d39b33 attach ECC pins Miodrag Milanovic 2025-08-29 12:47:57 +0200
b6287fed67 fix cluster setting for cascade mode Miodrag Milanovic 2025-08-29 12:41:58 +0200
42924dec69 Name RAM cells Miodrag Milanovic 2025-08-29 12:30:33 +0200
f25088bdd1 optmize remapping halfs Miodrag Milanovic 2025-08-29 12:22:25 +0200
93c15da8fa move code arround Miodrag Milanovic 2025-08-29 09:22:13 +0200
b452e0e12a Cleanups Miodrag Milanovic 2025-08-29 09:00:42 +0200
8c770dbfb0 Gowin. Fix the style. YRabbit 2025-08-29 00:10:16 +1000
17ca049efd gatemate: Split BRAMs into halfs Miodrag Milanovic 2025-08-28 15:11:21 +0200
224331a2ec Gowin. Optimize ALU wiring YRabbit 2025-08-28 17:15:17 +1000
e1ba78094f gatemate: clean data bitmask Miodrag Milanovic 2025-08-27 12:28:58 +0200
8ab9301dc4 clangformat Miodrag Milanovic 2025-08-27 10:37:39 +0200
2b203d21ae gatemate: add missing RAM port mapping Miodrag Milanovic 2025-08-27 10:37:10 +0200
52254dca35

Gowin. Add ROM16 primitive. (#1542) YRabbit 2025-08-27 15:21:38 +1000
1fffbe526e Gowin. Add ROM16 primitive. YRabbit 2025-08-27 14:31:44 +1000
d966fc5dcb

Gowin. Implement ALU for the GW5A series. (#1541) YRabbit 2025-08-27 00:17:55 +1000
0a7cbe1cd7

router2: iteratively reserve arc driver wires, too (#1539) Lofty 2025-08-26 15:17:11 +0100
f33fdf02b7 gatemate: update bounding box Miodrag Milanovic 2025-08-26 13:52:18 +0200
7fd9fae075 Gowin. Implement ALU for the GW5A series. YRabbit 2025-08-26 19:37:50 +1000
ca4f727ffc gatemate: fix CI/CO RAM connections Miodrag Milanovic 2025-08-25 12:24:46 +0200
d0858b04f2 router2: iteratively reserve arc driver wires, too Lofty 2025-08-20 10:42:15 +0100
84234e7d79 gatemate: delay, assign proper RAM clock Miodrag Milanovic 2025-08-25 10:55:19 +0200
d796cc720b clangformat Miodrag Milanovic 2025-08-22 11:08:39 +0200
6a598b945e

gatemate: add iopath delays (#1537) Miodrag Milanović 2025-08-22 11:07:34 +0200
2b35884a19 no need for return Miodrag Milanovic 2025-08-21 15:35:31 +0200
07e2d0952b support strings as options Miodrag Milanovic 2025-08-21 15:34:27 +0200
e598b2f4d9

gatemate: special case RAMIO when needed (#1536) Miodrag Milanović 2025-08-21 15:11:08 +0200
e92b6dcb66 remove short name options Miodrag Milanovic 2025-08-21 15:09:40 +0200
c1e01bd3b9 Map few more timings Miodrag Milanovic 2025-08-21 14:39:36 +0200
156fe86843 gatemate: special case RAMIO when needed Miodrag Milanovic 2025-08-21 14:20:28 +0200
7687a83e44 cleanup Miodrag Milanovic 2025-08-21 11:34:26 +0200
16251795e0 cleanup Miodrag Milanovic 2025-08-18 13:58:21 +0200
2c787da635 Add more IOPATHs Miodrag Milanovic 2025-08-18 11:01:47 +0200
728d926296 Added some RAM timings Miodrag Milanovic 2025-08-15 16:18:25 +0200
c5650c652f clockToQ Miodrag Milanovic 2025-08-15 14:46:42 +0200
13301deb2f Disable not used paths Miodrag Milanovic 2025-08-15 13:31:33 +0200
7df7c6bd2a cover all primitives Miodrag Milanovic 2025-08-15 10:53:57 +0200
e0280cba1e return true only if exists Miodrag Milanovic 2025-08-15 10:23:14 +0200
4d09905808 help figure out some ram paths Miodrag Milanovic 2025-08-15 09:53:58 +0200
05c7e14c46 Fix logic loops Miodrag Milanovic 2025-08-14 16:15:49 +0200
e3cbfe96f4 Add IOSEL delays Miodrag Milanovic 2025-08-14 13:58:10 +0200
1320e3c067 Fixes for IO Miodrag Milanovic 2025-08-14 13:36:49 +0200
603fa0300b wip Miodrag Milanovic 2025-08-13 13:37:05 +0200
13eac1bb77 wip Miodrag Milanovic 2025-08-13 11:31:13 +0200
3b3361a848 proper place for assignArchInfo Miodrag Milanovic 2025-08-13 10:51:55 +0200
b14b27d082 wip Miodrag Milanovic 2025-08-13 09:20:43 +0200
984c3ff8d6 Added helpers Miodrag Milanovic 2025-08-12 15:09:38 +0200
4b0afc60a7 wip Miodrag Milanovic 2025-08-12 13:35:42 +0200
024401d271 Add separate file for delay handling Miodrag Milanovic 2025-08-11 14:01:41 +0200
275bb035f8 Add constants for needed timings Miodrag Milanovic 2025-08-11 12:47:25 +0200
1c381d1279 Import all timing data Miodrag Milanovic 2025-08-11 12:27:42 +0200
b1504df5b2 Import some new data Miodrag Milanovic 2025-08-08 12:31:49 +0200
c785f252dd clangformat Miodrag Milanovic 2025-08-08 10:36:58 +0200
711a807d98 Timing Miodrag Milanovic 2025-07-30 14:17:26 +0200
82f8ff7cad

himbaechel: Extend API to enable cell delay override (#1535) Miodrag Milanović 2025-08-20 06:32:18 +0200
5be8c11d0a himbaechel: Extend API to enable cell delay override Miodrag Milanovic 2025-08-18 13:46:25 +0200
322ad920b3

Gowin. Enable GW5A series. (#1534) YRabbit 2025-08-15 15:12:09 +1000
1b0b459e36 Gowin. Enable GW5A series. YRabbit 2025-08-15 05:41:39 +1000
178021959c Gowin. Change the way DFF 6&7 presence is checked. YRabbit 2025-08-14 21:19:39 +1000
2d0ad9f9b1 Gowin. Use two additional DFFs. YRabbit 2025-08-14 13:53:24 +1000
268d649613 Gowin. Change the way DFF 6&7 presence is checked. YRabbit 2025-08-14 21:19:39 +1000
95ab16f380

gatemate: add IOSEL as separate primitive (#1533) Miodrag Milanović 2025-08-14 12:20:24 +0200
33607ba305 gatemate: add IOSEL as separate primitive Miodrag Milanovic 2025-08-14 11:54:09 +0200
10f899701f Gowin. Use two additional DFFs. YRabbit 2025-08-14 13:53:24 +1000
b0626280e9 Change Hash Embed check to check for erroneous signed #embed Will MacCormack 2025-08-09 12:06:17 -0500
fd1b2289f5 Change Hash Embed check to check for erroneous signed #embed Will MacCormack 2025-08-09 12:06:17 -0500