fba71bd182
clangformat
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Signed-off-by: gatecat <gatecat@ds0.me>
2021-03-03 10:39:47 +00:00
71b92cb813
Update FPGA interchange README.
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Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2021-02-26 11:01:22 -08:00
78748a67be
For now just return false in the site router.
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Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2021-02-26 11:01:22 -08:00
cfa449c3f3
Initial LUT rotation logic.
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Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2021-02-26 11:01:22 -08:00
9cbfd0b967
Add counter test.
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Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2021-02-26 11:01:22 -08:00
23413a4d12
Fix compiler warnings introduced by -Wextra
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Signed-off-by: gatecat <gatecat@ds0.me>
2021-02-25 15:15:25 +00:00
a30043c8da
Fix assorted bugs in FPGA interchange.
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Fixes:
- Only use map constant pins during routing, and not during placement.
- Unmapped cell ports have no BEL pins.
- Fix SiteRouter congestion not taking into account initial expansion.
- Fix psuedo-site pip output.
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2021-02-23 14:09:28 -08:00
184665652e
Finish dedicated interconnect implementation.
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Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2021-02-23 14:09:28 -08:00
5574455d2a
Working FF example now that constant merging is done.
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Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2021-02-23 14:09:28 -08:00
2fc353d559
Add initial logic for handling dedicated interconnect situations.
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Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2021-02-23 14:09:28 -08:00
cd8297f54d
Move RapidWright git URI back to upstream.
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Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2021-02-23 14:09:28 -08:00
5c6e231412
Remove some signedness warnings.
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Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2021-02-23 14:09:28 -08:00
46b38f8a40
Fix reference copy.
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Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2021-02-23 14:09:27 -08:00
3ccb164f2a
Run "make clangformat".
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Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2021-02-23 14:09:27 -08:00
15459cae91
Initial working constant network support!
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Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2021-02-23 14:09:27 -08:00
cf554f9338
Add constant network test case.
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Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2021-02-23 14:09:27 -08:00
3e5a23ed5b
Add tests to confirm constant routing import.
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Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2021-02-23 14:09:27 -08:00
761d9d9229
Correct some bugs in the create_bba Makefile.
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Also add debug_test target to debug archcheck.
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2021-02-23 14:09:27 -08:00
40df4f4f65
Add initial constant network support to FPGA interchange arch.
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Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2021-02-23 14:09:27 -08:00
423a10bc31
Change CellInfo in getBelPinsForCellPin to be const.
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Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2021-02-23 14:08:54 -08:00
7922b3bfc4
Replace DelayInfo with DelayPair/DelayQuad
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This replaces the arch-specific DelayInfo structure with new DelayPair
(min/max only) and DelayQuad (min/max for both rise and fall) structures
that form part of common code.
This further reduces the amount of arch-specific code; and also provides
useful data structures for timing analysis which will need to delay
with pairs/quads of delays as it is improved.
While there may be a small performance cost to arches that didn't
separate the rise/fall cases (arches that aren't currently separating
the min/max cases just need to be fixed...) in DelayInfo, my expectation
is that inlining will mean this doesn't make much difference.
Signed-off-by: gatecat <gatecat@ds0.me>
2021-02-19 11:31:33 +00:00
c21e23b3eb
Fix sign mismatch.
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Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2021-02-18 14:08:22 -08:00
e138a6c56d
Do some spell checking on site_router.cc
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Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2021-02-18 13:34:06 -08:00
4766e889c0
Add some utility methods for site instance access.
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Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2021-02-18 13:26:52 -08:00
532954847a
Update README's with latest instructions and features.
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Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2021-02-18 13:01:42 -08:00
8ef5411f70
Add utility targets for getting plain text outputs.
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Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2021-02-17 12:03:17 -08:00
b3dcc9d507
Add IOSTANDARD to ports.
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Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2021-02-17 12:03:17 -08:00
5833c90210
Emit fixed attributes to output physical netlist.
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Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2021-02-17 12:03:17 -08:00
558a753d3d
Refactor "get only from iterator" to a utility.
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Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2021-02-17 12:03:17 -08:00
9e0ca72827
Keep all build artifacts under create_bba/build.
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Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2021-02-17 12:03:16 -08:00
f9bd692f75
Change how package pin IO sites are selected.
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The first site type that matches is now selected, under the premise that
the early site types are more general.
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2021-02-17 12:03:16 -08:00
cc687b3b72
Change makefiles to build a FPGA interchange BBA.
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Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2021-02-17 12:03:16 -08:00
5a7f83c705
Add examples invoking FPGA interchange nextpnr.
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Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2021-02-17 12:03:16 -08:00
7c1544f4d8
Continue fixes.
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Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2021-02-17 12:03:16 -08:00
6f1c835221
Disable traversal limit when reading logical netlist.
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Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2021-02-17 12:03:16 -08:00
c385321248
Add initial site router.
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This site router likely cannot handle the full problem space. It may
need to be replaced with a more generalize approach as testing
continues.
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2021-02-17 12:03:16 -08:00
a7421399f7
Working on standing up initial constraints system.
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Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2021-02-17 12:03:16 -08:00
399c24c805
clangformat
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Signed-off-by: gatecat <gatecat@ds0.me>
2021-02-17 10:45:23 +00:00
da1ecf0813
Merge pull request #586 from litghost/add_cell_bel_mapping_only
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Add Cell -> BEL Pin maps to FPGA interchange arch.
2021-02-17 10:16:45 +00:00
26a187e5eb
Require `--package` when arch BBA contains multiple packages.
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Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2021-02-16 14:00:01 -08:00
bb4fa7af5b
[FPGA Interchange] Add Cell -> BEL Pin maps.
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This also expands the FPGA interchange Arch BBA to include placement
constraints, but doesn't implement them yet.
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2021-02-16 09:37:19 -08:00
c7c13cd95f
Remove isValidBelForCell
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This Arch API dates from when we were first working out how to
implement placement validity checking, and in practice is little used by
the core parts of placer1/HeAP and the Arch implementation involves a
lot of duplication with isBelLocationValid.
In the short term; placement validity checking is better served by the
combination of checkBelAvail and isValidBelForCellType before placement;
followed by isBelLocationValid after placement (potentially after
moving/swapping multiple cells).
Longer term, removing this API makes things a bit cleaner for a new
validity checking API.
Signed-off-by: gatecat <gatecat@ds0.me>
2021-02-16 13:31:36 +00:00
2c7ee44046
Move CMake logic into fpga-interchange-schema.
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Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2021-02-15 09:54:58 -08:00
6b04fd1524
Small fixes from review.
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Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2021-02-15 09:54:58 -08:00
664407089b
Add FPGA interchange frontend and backend.
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Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2021-02-15 09:54:58 -08:00
1b6cdce925
Merge pull request #575 from YosysHQ/gatecat/belpin-2
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Support for cell pin to bel pin mappings
2021-02-15 09:38:22 +00:00
82ab3c1aad
Run "make clangformat".
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Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2021-02-12 10:31:05 -08:00
8a860857ea
Remove capnp and libz for XDC parser PR.
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Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2021-02-12 10:31:05 -08:00
c96d0f225c
Refactor XDC parser into a little class for testing purposes.
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Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2021-02-12 10:31:04 -08:00
d987bd2997
Add unknown handles to convert [0] to "[0]".
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Tcl reads something like "set port [get_ports x[0]]" as "invoke proc 0
with zero arguments", rather than just "[0]". To prevent exposing
non-Tcl users this, "[<number>]" just return themselves.
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2021-02-12 10:31:04 -08:00
gatecat
Keith Rothman