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78 Commits

Author SHA1 Message Date
Miodrag Milanović 21bfda4165
gatemate: fix fourgroup for multi die (#1550) 2025-09-03 12:20:11 +02:00
Miodrag Milanović 3eb682bcbb
gatemate: use CPE bridge (#1538) 
* Add bridge support

* Use bridge only if CPE is unused

* do not use CPE_MULT for MUX routing

* Fixed and documented

* delay for CPE_BRIDGE

* Convert bridge pips into bels

Co-authored-by: Miodrag Milanovic <mmicko@gmail.com>

* recursively reassign bridges

* reconnect cell ports to new nets

* handle inversion bits

* sort data in output for easier compare

* one to be removed after testing

* debug message

* Remove need for notifyPipChange

* use same logic for detecting bridge pips

* make sure that the pip used is the one assigned

* one wire may feed multiple ports

* remove #if

* clean up wire binding

* add debugging

* fix

* clangformat

* put back to error

* use tile instead of getting name out of bel/pip

* bump chipdb

* adressing review comments

* Addressed last one

---------

Co-authored-by: Lofty <dan.ravensloft@gmail.com>
 2025-09-02 18:00:01 +02:00
Miodrag Milanović 4e4f4ab113
gatemate: update bounding box (#1548) 2025-09-02 14:04:28 +02:00
Miodrag Milanović 0399b8865e
gatemate: Enable placing RAM halfs (#1544) 
* gatemate: Split BRAMs into halfs

* Cleanups

* move code arround

* optmize remapping halfs

* Name RAM cells

* fix cluster setting for cascade mode

* attach ECC pins

* rewire global clocks

* bump chip database version

* Fix KEEPER setting

* Fix conflict check

* cleanup
 2025-09-02 08:03:22 +02:00
Miodrag Milanovic e1ba78094f gatemate: clean data bitmask 2025-08-27 12:28:58 +02:00
Miodrag Milanovic 2b203d21ae gatemate: add missing RAM port mapping 2025-08-27 10:37:10 +02:00
Miodrag Milanovic ca4f727ffc gatemate: fix CI/CO RAM connections 2025-08-25 12:24:46 +02:00
Miodrag Milanovic 84234e7d79 gatemate: delay, assign proper RAM clock 2025-08-25 10:55:19 +02:00
Miodrag Milanović 6a598b945e
gatemate: add iopath delays (#1537) 
* Timing

* clangformat

* Import some new data

* Import all timing data

* Add constants for needed timings

* Add separate file for delay handling

* wip

* Added helpers

* wip

* proper place for assignArchInfo

* wip

* wip

* Fixes for IO

* Add IOSEL delays

* Fix logic loops

* help figure out some ram paths

* return true only if exists

* cover all primitives

* Disable not used paths

* clockToQ

* Added some RAM timings

* Add more IOPATHs

* cleanup

* cleanup

* Map few more timings

* remove short name options

* support strings as options

* no need for return
 2025-08-22 11:07:34 +02:00
Miodrag Milanović e598b2f4d9
gatemate: special case RAMIO when needed (#1536) 2025-08-21 15:11:08 +02:00
Miodrag Milanović 95ab16f380
gatemate: add IOSEL as separate primitive (#1533) 2025-08-14 12:20:24 +02:00
Lofty 5355222e09 Revert "gatemate: don't place cells all at once (#1528)" 
This reverts commit 2d393c2487.
 2025-08-09 04:35:20 +01:00
Lofty 2d393c2487
gatemate: don't place cells all at once (#1528) 2025-08-08 18:19:42 +02:00
Lofty 0ad43e6ec7
gatemate: remove placement density restriction (#1527) 2025-08-08 17:02:56 +02:00
Lofty 8938c73fc9
Merge pull request #1524 from YosysHQ/lofty/gatemate-mult-router 
gatemate: multiplier router
 2025-08-05 11:20:25 +01:00
Miodrag Milanovic 6b11a82d04 cleanup 2025-08-04 14:28:43 +02:00
Miodrag Milanovic f0e03ed6e7 cleanup 2025-08-04 14:23:18 +02:00
Miodrag Milanovic 89e7e059d8 cleanup 2025-08-04 13:55:19 +02:00
Miodrag Milanovic eb77362b97 Added logs under debug, and removed include for idstring.h 2025-08-04 13:50:19 +02:00
Miodrag Milanovic 88f52bcaba Fix multipliers on hardware 2025-08-04 13:26:26 +02:00
Lofty 60f3c25cb0 refactor inversion checker 2025-08-02 15:23:56 +01:00
Lofty fe7546fda5 Multiplier routing needs priority over clocks 2025-08-02 14:00:25 +01:00
Miodrag Milanovic 0810a9a243 More multiplier fixes 2025-08-02 13:04:13 +02:00
Miodrag Milanovic 6a3c4a2dca Enable pack_mult 2025-08-01 17:47:07 +02:00
Miodrag Milanovic 1748f38aad Add MULT_INVERT property 2025-08-01 17:46:48 +02:00
Lofty d26fc19724 clangformat 2025-08-01 16:46:22 +01:00
Miodrag Milanovic 49001df290 Fix when width is 1 2025-08-01 14:46:54 +02:00
Miodrag Milanovic da5d42dc9d Add missing connection 2025-08-01 12:25:22 +02:00
Lofty d53f774078 re-disable multiplier packing 2025-07-31 14:54:43 +01:00
Lofty 341e288488 fix swapped B inputs 2025-07-31 14:50:36 +01:00
Miodrag Milanovic 7d8b7da20b Add missing connection 2025-07-29 14:01:07 +02:00
Miodrag Milanović 7e68bea863
gatemate: fix SER_CLK wiring from CLKIN to PLL (#1523) 
* gatemate: fix SER_CLK wiring from CLKIN to PLL

* fix some output formatting

---------

Co-authored-by: Patrick Urban <patrick.urban@web.de>
 2025-07-29 11:26:49 +02:00
Lofty d26aa342b7 bugfix for x2y2 in8 binding a pip twice 2025-07-29 09:37:45 +01:00
Lofty ac8a12aee5 bugfix for number of hops 2025-07-29 09:37:45 +01:00
Lofty ff9fa6f4cc route comments 2025-07-29 09:37:45 +01:00
Lofty 95b32a2b56 working diagonal router; unhappy inversion checker 2025-07-29 09:37:45 +01:00
Lofty 9837b6f676 current progress (broken diagonal router) 2025-07-29 09:37:45 +01:00
Lofty 80664e55b7 current progress (fixed routing done?) 2025-07-29 09:37:45 +01:00
Lofty 78b614ed31 current progress 2025-07-29 09:37:45 +01:00
Lofty 1576703937 current progress (route zero driver too) 2025-07-29 09:37:45 +01:00
Lofty d1f80ca5bb current progress 2025-07-29 09:37:45 +01:00
Lofty 4cf33090a9 current progress 2025-07-29 09:37:45 +01:00
Lofty 8637e3bc18 heavy refactoring 2025-07-29 09:37:45 +01:00
Lofty 56e1452d31 refactor common routes 2025-07-29 09:37:45 +01:00
Lofty 90f5f719f3 current progress 2025-07-29 09:37:45 +01:00
Lofty 530a08606b current progress 2025-07-29 09:37:45 +01:00
Lofty 0829b46e9b move multiplier router to its own file 2025-07-29 09:37:45 +01:00
Lofty 0533a4c12b fixed missing pip 2025-07-29 09:37:45 +01:00
Hannah Ravensloft 8047369347 better inversion verification 2025-07-29 09:37:45 +01:00
Hannah Ravensloft f2c736ef81 Beginnings of the multiplier router 2025-07-29 09:37:45 +01:00