* CPE mapping improvements
* Use CP_OUT for adders
* Fixes
* Small fixes
* Cleanups
* Cleanup
* Cleanups
* Fixes
* Fixes
* Optimize
* Cleanup
* clangformat
* Cleanup
* Cleanup
* Bump required version of database
* Cleanup
* Resolve name conflicts
* Fix signal routing
* Make CPE_LATCH separate
* Add more timings models, need updated values
* Fixed warning
* multiplier support from lofty/gatemate-mult
* explicitly zero some params in B passthrough
* comment the relevant CPE inputs in check_multipliers
* Rename some of bels
* remove _lower from name
* refactor multiplier checking
* Revert "remove _lower from name"
This reverts commit daa1041bdf.
* Fixe net name to be unique
* Make sure we at least generate bitstream with all info
* Simplify zero
* Bounded cell type in gui
* typo fix
* Remove A passthrough inversion option
* Clean up CarryGenCell config
* Update a passthru to use new primitives
* Cleanup for adders
* Clean up MsbRoutingCell
* Cleanup
* Refactor A connection code
* Make it more as in PR #1513
* Added cplines to bpassthru and fixed constant driver for A
* Add parts
* Added comp out connections
* clangformat
* clangformat
* Clean up B passthrough connections
* wire up a bunch of intermediate signals
* Bit of cleanup
* handing of C_EN_IN
* C_EN_CIN fixes
* connect f_route to its lines
* fix cite for FRoutingCell
* fixup, oops
* connect multfab to its lines
* Commented line
* Connect CPOUTs
* Handle C_I params
* connect CINY1 for CarryGenCell
* fix carry gen CINX
* Update L2T4 model
* Updates for ADDCIN
* clangformat
* fix some issues with multfab and f_route
* look at C_I when doing inversion
* Only set some C_I signals when used
* Fix one more place
* do not use cplines so we can merge in one cell
* Cover cases that could be optimized out
* clangformat
* Cleanups
* Disable multiplier usage for now
---------
Co-authored-by: Lofty <dan.ravensloft@gmail.com>
Use loop enumeration of PIPs instead of direct name construction for the
upper and lower ends of the segment wire.
Also do not allow clock wires for segments.
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* SER_CLK support
* Update constids
* wip
* CLK_FEEDBACK
* Handle SER_CLK and SER_CLK_N
* clangformat
* Cleanup
* Use _ as separator for PLL CFGs
* Remove unused clocking cells
* Do not use same name for IO models
* Fix IDDR merge
* Cleanup
* Properly handle user global signals
* Move signal inversion in bitstream creation
* Start adding multi die support
* Display die location for pins used
* Do not use constant s as locations
* Cleanup SB_DRIVE handling
* Use DDR locations from chip database
* Place only in prefered die for now
* Set D2D
* Fixed typos
A segment router replaces the source-to-sink connection by
general-purpose PIPs with bus-branch segment network connections.
The problem arises when the source is connected to the sinks directly
without switching as in the case of LUT->DFF, such wires should be left
as is, which is what this PR does.
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* gatemate: clock router
Co-authored-by: Miodrag Milanovic <mmicko@gmail.com>
* Re-add clock router pip binding
* Refactoring
* Require globals to use a BUFG
* Fix misunderstanding of GPIO/RAM clocking
* Add plane info to chipdb
* Force clock routing along a specific plane
* Remove overly-limiting condition
* Move clock router into its own file
* Clock router based on delay
* Refine clock router conditions
* More detailed clock routing output
* Clean up debug messages
* clangformat
---------
Co-authored-by: Miodrag Milanovic <mmicko@gmail.com>
Fill in the delays for PIP classes related to HCLK and IODELAY. Also:
- if clock routing fails, we try to use the next fastest mechanism - segment networks;
- fixing harmless typos.
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* Initial code for GateMate
* Initial work on forming bitstream
* Add CCF parsing
* Use CCF to set IO location
* Propagate errors
* Restructure code
* Add support for reading from config
* Start adding infrastructure for reading bitstream
* Fix script
* GPIO initial work
* Add IN1->RAM_O2 propagation
* Fixed typo
* Cleanup
* More parameter checks
* Add LVDS support
* Cleanup
* Keep just used connections for now
* Naive lut tree CPE pack
* Naive pack CC_DFF
* pack DFF fixes
* Handle MUX flags
* Fix DFF pack
* Prevent pass trough issues
* Cleanup
* Use device wrapper class
* Update due to API changes
* Use pin connection aliases
* Start work on BUFG support
* Fix CC_L2T5 pack
* Add CPE input inverters
* Constrain routes to have correct inversion state
* Add clock inversion pip
* Added MX2 and MX4 support
* Fix script
* BUFG support
* debug print if route found with wrong polarity
* Some CC_DFF improvements
* Create reproducible chip database
* Simplify inversion of special signals
* Few more DFF features
* Add forgotten virtual port renames
* Handle muxes with constant inputs
* Allow inversion for muxes
* cleanup
* DFF input can be constant
* init DFF only when needed
* cleanup
* Add basic PLL support
* Add some timings
* Add USR_RSTN support
* Display few more primitives
* Use pass trough signals to validate architecture data
* Use extra tile information from chip database
* Updates needed for a build system changes
* Implement SB_DRIVE support
* Properly named configuration bits
* autogenerated constids.inc
* small fix
* Initial code for CPE halfs
* Some cleanup
* make sure FFs are compatible
* reverted due to db change
* Merge DFF where applicable
* memory allocation issue
* fix
* better MX2
* ram_i handling
* Cleanup MX4
* Support latches
* compare L_D flag as well
* Move virtual pips
* Naive addf pack
* carry chains grouping
* Keep chip database reproducible
* split addf vectors
* Block CPEs when GPIO is used
* Prepare placement code
* RAM_I/RAM_O rewrite
* fix ram_i/o index
* Display RAM and add new primitives
* PLL wip code
* CC_PLL_ADV packing
* PLL handling cleanup
* Add PLL comments
* Keep only high fan-out BUFG
* Add skeleton for tests
* Utilize move_ram_o
* GPIO wip
* GPIO wip
* PLL fixes
* cleanup
* FF_OBF support
* Handle FF_IBF
* Make SLEW FAST if not defined as in latest p_r
* Make sure FF_OBF only driving GPIO
* Moved pll calc into separate file
* IDDR handling and started ODDR
* Route DDR input for CC_ODDR
* Notify error in case ODDR or IDDR are used but not with I/O pin
* cleanup for CC_USR_RSTN
* Extract proper RAM location for bitstream
* Code cleanup
* Allow auto place of pads
* Use clock source flag
* Configure GPIO clock signals
* Handle conflicting clk
* Use BUGF in proper order
* Connected CLK, works without but good for debugging
* CC_CFG_CTRL placement
* Group RAM data 40 bytes per row
* Write BRAM content
* RAM wip
* Use relative constraints from chipdb
* fix broken build
* Memory wip
* Handle custom clock for memories
* Support FIFO
* optimize move_ram_io
* Fix SR signal handling acorrding to findings
* set placer beta
* Pre place what we can
* Revert "debug print if route found with wrong polarity"
This reverts commit cf9ded2f18.
* Revert "Constrain routes to have correct inversion state"
This reverts commit 795c284d48.
* Remove virtual pips
* Implement post processing inversion
* ADDF add ability to route additional CO
* Merge two ADDFs in one CPE
* Added TODO
* clangformat
* Cleanup
* Add serdes handling in config file
* Cleanup
* Cleanup
* Cleanup
* Fix in PLL handling
* Fixed ADDF edge case
* No need for this
* Fix latch
* Sanity checks
* Support CC_BRAM_20K merge
* Start creating testing environment
* LVDS fixes
* Add connection helper
* Cleanup
* Fix tabs
* Formatting fix
* Remove optimization tests for now
* remove read_bitstream
* removed .c_str()
* Removed config parsing
* using snake_case
* Use bool_or_default where applicable
* refactored bitstream write code
* Add allow-unconstrained option
* Update DFF related messages
* Add clock constraint propagation
---------
Co-authored-by: Lofty <dan.ravensloft@gmail.com>
* Gowin. BUGFIX Use a separate net for segment gates
We use a temporary separate small network (typically 2 - 3 sinks) for
routing from the segment network source to the segment gate. This fixes
the rare but unpleasant case of self-intersection when a route to a gate
is routed using PIPs after the gate, this is no longer allowed when
using a separate small network.
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* Gowin. Fix style.
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
---------
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
DLLDLY is the clock delay primitive that adjust the input clock
according to the DLLSTEP signal and outputs the delayed clock.
These primitives are associated with clock pins and are "tapped" between
the output of this IBUF and the clock networks, leaving the possibility
to connect to the original unshifted signal as well, although the latter
is not very practical because it is no longer possible to use fast
wires.
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
Gowin chips have an interesting mechanism - wires that run vertically
through several rows (at least 10) in each column of the chip. In each
row a particular wire has branches to the left and right, covering on
average 4 neighboring cells in the row. For lack of a better term, I
further call such a wire a segment.
So a segment can provide a direct connection in a local rectangle. There
are no special restrictions on the sinks, so segment networks can be
used for ClockEnable, LocalSetReset, as well as for LUT and DFF inputs.
The sources are not so simple - the sources can be the upper or lower
end of the segment, which in theory can lead to unfortunate consequences
if the signal is applied from both ends.
The matter is complicated by the fact that there are default
connections, i.e. in the absence of any set fuse the segment input is
still connected to something (VCC for example) and to disable the unused
end of the segment you need to set a special combination of fuses.
Taking into account which end of which segment is used is one of the
tasks of this router. In addition, segment ends can physically coincide
with PLL, DSP and BSRAM inputs, which can also lead to unexpected
effects. Some of these things are tracked when generating the base, some
in this router, some when packing in gowin_pack.
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
Adds the ability to use high-speed clock lines (together with CLKDIV2
type frequency dividers operating on them) as sieve signals for the
CLKIN and CLKFB inputs of the rPLL and PLLVR primitives (these cover the
full range of supported Gowin chips).
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* Gowin. Add I3C io buffer.
A buffer is added that can operate as a normal IOBUF in PUSH-PULL mode
or switch to open-drain IOBUF mode.
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* Gowin. Turn a variable into a set of flags
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
---------
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
Adds output (MIPI_OBUF and MIPI_OBUF_A) and input (MIPI_IBUF) primitives
to allow the use of “real” MIPI (not emulation) ports capable of
operating in both HS and LP modes.
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
This is useful for certain cross-compilation workloads, and to cache
rarely changing build products.
To use this functionality, build e.g. as follows:
cmake . -B build-export -DEXPORT_BBA_FILES=../bba-files -DARCH=all
cmake --build build-export -t nextpnr-all-bba
cmake . -B build-import -DIMPORT_BBA_FILES=../bba-files -DARCH=all
cmake --build build-import
Two user-visible changes were made:
* `-DUSE_RUST` is replaced with `-DBUILD_RUST`, by analogy with
`-DBUILD_PYTHON`
* `-DCOVERAGE` was removed as it doesn't work with either modern GCC
or Clang
Primarily, this commit makes both of them use the `BBAsm` functions
to build and compile `.bba` files.
In addition, Himbaechel targets are now aligned with the rest in
how they are configured: instead of having all uarches enabled with
all of the devices disabled (the opposite of the rest of nextpnr),
uarches must be enabled explicitly but they come with all devices
enabled (except for Xilinx, which does not have a list of devices).
Miodrag Milanovic
José Miguel Sánchez García
myrtle
YRabbit
Lofty
Catherine