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1178 Commits

Author SHA1 Message Date
Maciej Kurc 76f5874ffc Brought back printout of critical path source file references, added clk-to-q, source and setup segment types 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2021-09-29 10:16:45 +02:00
Maciej Kurc 1ed692aca9 Shifted moving of data containers after printing 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2021-09-28 18:01:30 +02:00
Maciej Kurc 9018782eaa Added a commandline option controlled writeout of per-net timing details 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2021-09-28 17:42:51 +02:00
Maciej Kurc a9df3b425f Added description of the JSON report structure. 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2021-09-28 17:42:51 +02:00
Maciej Kurc 6deff56e83 Moved timing result report storage to the context, added its writeout to the current utilization and fmax report 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2021-09-28 17:42:51 +02:00
Maciej Kurc c6dc1f535a Added reporting critical paths in JSON format 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2021-09-28 17:42:51 +02:00
Maciej Kurc d8571b6c00 Decoupled critical path report generation from its printing 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2021-09-28 17:42:51 +02:00
Maciej Kurc 12adbb81b1 Switched to JSON format for timing analysis report 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2021-09-28 17:42:51 +02:00
Maciej Kurc 99ae5ef38e Added writing a CSV report with timing analysis of each net branch 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2021-09-28 17:42:51 +02:00
gatecat 0b0baf3446 idstring: Add 'in' function 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-09-27 19:18:40 +01:00
gatecat 535b2490c4
Merge pull request #812 from antmicro/MacroCells 
Convert macros to clusters for better placement
 2021-09-27 17:50:55 +01:00
Maciej Dudek ea489f6d93 Fix small isses and code formatting 
Signed-off-by: Maciej Dudek <mdudek@antmicro.com>
 2021-09-27 16:16:33 +02:00
gatecat ab6990f908 router2: Allow overriding resource costs 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-09-24 19:11:37 +01:00
Maciej Dudek 3cd459912a Adding MacroCell placement 
Signed-off-by: Maciej Dudek <mdudek@antmicro.com>
 2021-09-23 15:43:23 +02:00
Maciej Dudek fdcfe8cd81 Adding support for MacroCells 2021-09-23 15:43:23 +02:00
gatecat d9a71083e1
Merge pull request #825 from antmicro/chain_swap_fix 
Fix chain swap
 2021-09-23 14:10:46 +01:00
Maciej Dudek 8c97cbe341 Fix chain swap 
Issue was due to dest_bels being not cleared between clusters unbindes, causing
newly bind bels to be unbinded and having their old bel value changed to new bel value.
Then when swap failed 2 cells were being bind to a single bel.

I tested leaving dest_bels in the function scope and moving it to the loop scope.
Code with dest_bels in the loop scope was faster than leaving it in the function scope,
and checking if the cell is in the processed cluster.

Signed-off-by: Maciej Dudek <mdudek@antmicro.com>
 2021-09-23 13:58:22 +02:00
gatecat 562d02196c python: Restore SIGINT handler while running a Python script 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-09-22 22:01:58 +01:00
gatecat 4d90850676 placer1: Remove redundant relative constraint check 
Macros with potentially inconsistent spacing are now permissible.

Signed-off-by: gatecat <gatecat@ds0.me>
 2021-09-22 13:14:45 +01:00
gatecat e926cddca2 placer1: Fix cluster swap cost updates 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-09-18 11:11:24 +01:00
gatecat 4730a4f339 timing: Always use max delay for required time 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-09-18 11:04:39 +01:00
gatecat 287a860283 timing: Fix slack for unconstrained clocks 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-09-18 10:43:19 +01:00
gatecat f119f56e63 placer1: Allow swapping chains with other chains 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-09-17 21:51:18 +01:00
gatecat 1e4f706ace command: Allow running Python on failure for state introspection 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-09-16 20:56:32 +01:00
gatecat d08fb255a2 router2: Fix uninitialised values 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-09-06 13:29:23 +01:00
gatecat 01b51fb715 router2: Fix explored count 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-09-02 17:08:54 +01:00
gatecat b85fe12234 python: Wrap PortRef by value 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-08-26 13:23:16 +01:00
gatecat de311e052f python: Allow querying route delays 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-08-23 20:51:53 +01:00
Sylvain Munaut df67783dd3 pybindings: Fix mapping for PortRefVector 
This is used by net.users for instance.

Removed by mistake in 4ac00af6fa

Fixes #799

Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
 2021-08-19 12:01:49 +02:00
gatecat f207068ee2 router2: Add experimental timing-driven ripup option 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-08-15 16:22:03 +01:00
gatecat 42522c492c router2: Alternative congestion cost schedule 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-08-15 16:22:03 +01:00
gatecat 2a856db72c router2: Adding some criticality heuristics 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-08-15 16:22:03 +01:00
gatecat 64f6b8bc67 router2: Improved bidir routing and data structures 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-08-15 16:22:03 +01:00
gatecat ef1fbfc651
Merge pull request #787 from YosysHQ/gatecat/report 
Add JSON utilisation and timing report
 2021-07-30 14:29:55 +01:00
gatecat b5a31d2e4e router2: Mark dest as visited during backwards routing 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-07-30 09:14:46 +01:00
gatecat 42f48b6dc0 router2: Improve debugability of pip conflicts 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-07-29 13:04:59 +01:00
gatecat d2007a386c common: Add JSON timing and utilisation report 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-07-29 12:53:23 +01:00
gatecat 4ac00af6fa basectx: Add a field to store timing results 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-07-29 12:52:13 +01:00
gatecat 504199e70e nexus: Fix routeing of global clocks that also drive fabric 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-07-28 15:35:19 +01:00
gatecat ce92cdf8e4 router2: Update route delays even when routes are congested 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-07-28 12:15:36 +01:00
gatecat 14c676ab49 timing: Allow overriding of route delays 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-07-28 11:20:28 +01:00
gatecat 0e3b25468c gui: Implement about dialog 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-07-25 12:06:51 +01:00
gatecat 08bbe173ce Fix definition of an empty IdStringList 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-07-20 15:51:04 +01:00
Alessandro Comodi 7abfeb11c3 interchange: xdc and place constr: address review comments 
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2021-07-12 17:17:57 +02:00
Alessandro Comodi d9668df818 interchange: add constraints constraints application routine 
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2021-07-12 16:45:08 +02:00
gatecat 76070a7647 timing: Fix out-of-bounds histogram bins in all cases 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-07-10 23:44:21 +01:00
gatecat 5b2db015a9
Merge pull request #752 from YosysHQ/gatecat/du-mem-error 
design_utils: Fix memory error
 2021-07-06 12:43:48 +01:00
gatecat 3d0facf119 design_utils: Fix memory error 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-07-06 11:35:27 +01:00
gatecat 31abefc8e4 interchange: Allow pseudo pip wires to overlap with bound site wires on the same net 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-07-06 10:38:08 +01:00
gatecat 6fe071ad1d router2: Dump pre-bound routes when routing fails in debug mode 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-07-06 10:21:31 +01:00
gatecat 86bc708299 clangformat 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-07-01 13:18:34 +01:00
Miodrag Milanovic 5c6b8a5f04 Preserve ArchArgs and reinit Context when applicable in GUI 2021-06-30 10:10:18 +02:00
gatecat 889c295baf sta: Fix a memory error introduced by the dict move 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-06-17 12:06:26 +01:00
gatecat ee65e6f32d
Merge pull request #724 from YosysHQ/gatecat/update-names 
Update deadnames and emails
 2021-06-12 14:07:47 +01:00
gatecat 2ffb081442 Fixing old emails and names in copyrights 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-06-12 13:22:38 +01:00
gatecat f9d3b99e63 HeAP: Fix memory error introduced by switch to dict 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-06-12 13:07:11 +01:00
gatecat 875004d300 gui: Don't destroy context when loading JSON 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-06-07 21:07:17 +01:00
gatecat dcbb322447 Remove redundant code after hashlib move 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-06-02 15:05:20 +01:00
gatecat eca1a4cee4 Use hashlib in most remaining code 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-06-02 15:05:20 +01:00
gatecat b8a68f5f35 Using hashlib in timing 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-06-02 15:05:20 +01:00
gatecat ecc19c2c08 Using hashlib in arches 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-06-02 15:05:19 +01:00
gatecat f4fed62c05 Use hashlib in routers 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-06-02 15:04:53 +01:00
gatecat 43b8dde923 Use hashlib in placers 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-06-02 15:04:49 +01:00
gatecat 579b98c596 Use hashlib for core netlist structures 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-06-02 14:27:56 +01:00
gatecat ff72454f83 Add hash() member functions 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-06-02 14:27:56 +01:00
gatecat 76ef768864 common: Import hashlib from Yosys 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-06-02 14:27:56 +01:00
gatecat 315a5733d2 timing: Fix use of uninitialised value 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-06-01 11:40:55 +01:00
gatecat 1595c07260 router2: Add heatmap by routing resource type 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-05-20 14:54:23 +01:00
gatecat 5a41d2070c Run clangformat 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-05-16 16:25:05 +01:00
gatecat 3bb94192d5 mistral: Tidying up 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-05-15 14:54:33 +01:00
gatecat f318898474 router2: Hacky workaround for slow Cyclone V convergence 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-05-15 14:54:33 +01:00
gatecat 511e46c40f router2: Reduce verbosity when debugging 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-05-15 14:54:33 +01:00
gatecat e5e2f7bc62 mistral: Add stub pack/place/route functions 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-05-15 14:54:33 +01:00
gatecat b1d3eb07c3 archcheck: Use old connectivity check for CycloneV 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-05-15 14:54:33 +01:00
gatecat 5d1b8bf744 cyclonev: Add names and archcheck fixes 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-05-15 14:54:33 +01:00
gatecat ee60e9c71c router2: Add some boundness statistics 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-05-12 12:18:58 +01:00
gatecat e9fdbf618c router2: Fix a typo 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-05-11 13:02:23 +01:00
gatecat b3b79122e1 command: Allow debug output for just placer or router 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-05-11 11:35:43 +01:00
gatecat 65c611da02 router2: Reserve wires in more complex cases 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-05-06 21:20:09 +01:00
gatecat 62613cb266 router2: Dynamicly expand bounding box based on congestion 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-05-06 19:04:24 +01:00
gatecat 0d6be6f474 Add stub cluster API impl for remaining arches 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-05-06 13:12:52 +01:00
gatecat 1bf202adcd base_arch: Fix typo in getClusterPlacement 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-05-06 12:23:28 +01:00
gatecat 14863bc04e Update placers to use new cluster APIs 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-05-06 11:47:07 +01:00
gatecat 6a3eacddd6 Add default base implementation of cluster API 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-05-06 11:47:06 +01:00
gatecat e1717bd771 Add BaseClusterInfo for base implementation 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-05-06 11:47:06 +01:00
gatecat b62dcc4bcc arch_api: Outline of new cluster API 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-05-06 11:47:06 +01:00
David Corrigan f5c2547952
Update bits.h 
Fixed the variable name for windows MSVC builds.
 2021-04-30 21:42:25 -05:00
gatecat dcb09ec8de interchange: Implement getWireType 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-04-30 11:07:31 +01:00
gatecat 6fbefb8f13
Merge pull request #681 from YosysHQ/gatecat/more-pybindings 
Add Python bindings for placement tests
 2021-04-15 11:16:31 +01:00
gatecat d4aac6586c Add Python bindings for placement tests 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-04-15 10:00:45 +01:00
gatecat d14db5c98f Fix utilisation report when bel buckets are used 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-04-15 09:24:27 +01:00
gatecat 4e346ecfba Hash table refactoring 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-04-14 10:30:19 +01:00
gatecat ece10c3e04 timing: Fix domain init when loops are present 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-04-13 09:23:08 +01:00
gatecat 5cd2a7f9c2
Merge pull request #674 from adamgreig/heap-spreader-fix 
HeAP: Skip high-strength cells in both cell loops
 2021-04-12 14:16:22 +01:00
Adam Greig 2fdf41ac01
HeAP: Skip high-strength cells in both cell loops. 
Previously only the first loop skipped cells with high belStrength,
but they can't be processed by the second loop either, so skip them
there too.
 2021-04-12 13:42:20 +01:00
gatecat 5b35329abb fast_bels: Don't return pointer that might become invalid 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-04-12 10:23:41 +01:00
Keith Rothman a519341112 Fix bug in router2 where router may give up too early. 
Was introduced in #612.  The logic before was intended to prevent the
router from terminating early when not using a bounding box, but the fix
in #612 simply removed that, meaning that the router might terminate
early incorrectly.  The solution here is to only use the toexplore
hysteric once a solution is found.

Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-04-06 10:22:47 -07:00
gatecat 8863b962fd interchange: Fix illegal placements 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-03-30 15:28:19 +01:00
Keith Rothman 77bc2f9130 Add initial handling of local site inverters and constant signals. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-03-25 17:20:09 -07:00
Keith Rothman 8a50b02b9b Use new parameter definition data in FPGA interchange processing. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-03-23 09:01:43 -07:00