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Merge pull request #1019 from antmicro/support-clock-relations

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Support cross-domain clock relations in timing analyser
This commit is contained in:
myrtle
2022-09-20 15:55:43 +02:00
committed by GitHub
parent 136ab81cbd 9000c41c4b
commit f4e6bbd383
4 changed files with 300 additions and 11 deletions
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nexus/arch.cc
+11 -4
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@@ -526,6 +526,15 @@ bool Arch::getCellDelay(const CellInfo *cell, IdString fromPort, IdString toPort
}
int index = get_cell_timing_idx(id_DCS, id_DCS);
return lookup_cell_delay(index, fromPort, toPort, delay);
} else if (cell->type == id_DCC) {
if (fromPort == id_CLKI && toPort == id_CLKO) {
// TODO: Use actual DCC delays
delay.rise.min_delay = 1;
delay.rise.max_delay = 1;
delay.fall.min_delay = 1;
delay.fall.max_delay = 1;
return true;
}
}
return false;
}
@@ -594,11 +603,9 @@ TimingPortClass Arch::getPortTimingClass(const CellInfo *cell, IdString port, in
return type;
} else if (cell->type == id_DCC) {
if (port == id_CLKI)
return TMG_CLOCK_INPUT;
else if (port == id_CLKO)
return TMG_GEN_CLOCK;
else if (port == id_CE)
return TMG_COMB_INPUT;
else if (port == id_CLKO)
return TMG_COMB_OUTPUT;
} else if (cell->type == id_DCS) {
// FIXME: Making inputs TMG_CLOCK_INPUT and the output TMG_CLOCK_GEN
// yielded in error in the timing analyzer. For now keep those as