luke
/
nextpnr
mirror of https://github.com/YosysHQ/nextpnr.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

cleanup

This commit is contained in:
Miodrag Milanovic 2025-12-18 09:49:36 +01:00
parent 1e00aa4a94
commit e5f2a62acf
5 changed files with 142 additions and 224 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

75
himbaechel/uarch/gatemate/delay.cc
View File

@ -90,47 +90,20 @@ bool GateMateImpl::getCellDelay(const CellInfo *cell, IdString fromPort, IdStrin
{
delay = DelayQuad{0};
static dict<IdString, IdString> map_upper = {
{ id_D0_00, id_IN1},
{ id_D1_00, id_IN2},
{ id_D0_01, id_IN3},
{ id_D1_01, id_IN4},
{ id_D0_10, id_IN1},
{ id_D1_10, id_IN3},
{id_OUT, id_OUT2},
{id_RAM_O, id_RAM_O2},
{id_RAM_I, id_RAM_I2},
{id_CPOUT, id_CPOUT2},
{id_D0_00, id_IN1}, {id_D1_00, id_IN2}, {id_D0_01, id_IN3}, {id_D1_01, id_IN4}, {id_D0_10, id_IN1},
{id_D1_10, id_IN3}, {id_OUT, id_OUT2}, {id_RAM_O, id_RAM_O2}, {id_RAM_I, id_RAM_I2}, {id_CPOUT, id_CPOUT2},
};
static dict<IdString, IdString> map_lower = {
{ id_D0_00, id_IN5},
{ id_D1_00, id_IN6},
{ id_D0_01, id_IN7},
{ id_D1_01, id_IN8},
{ id_D0_10, id_IN5},
{ id_D1_10, id_IN7},
{ id_D0_02, id_IN5},
{ id_D1_02, id_IN6},
{ id_D0_03, id_IN7},
{ id_D1_03, id_IN8},
{ id_D0_11, id_IN5},
{ id_D1_11, id_IN7},
{id_OUT, id_OUT1}, {id_RAM_O, id_RAM_O1}, {id_RAM_I, id_RAM_I1}, {id_CPOUT, id_CPOUT1},
{id_IN1, id_IN5}, {id_IN2, id_IN6}, {id_IN3, id_IN7}, {id_IN4, id_IN8},
{id_D0_00, id_IN5}, {id_D1_00, id_IN6}, {id_D0_01, id_IN7}, {id_D1_01, id_IN8}, {id_D0_10, id_IN5},
{id_D1_10, id_IN7}, {id_D0_02, id_IN5}, {id_D1_02, id_IN6}, {id_D0_03, id_IN7}, {id_D1_03, id_IN8},
{id_D0_11, id_IN5}, {id_D1_11, id_IN7}, {id_OUT, id_OUT1}, {id_RAM_O, id_RAM_O1}, {id_RAM_I, id_RAM_I1},
{id_CPOUT, id_CPOUT1}, {id_IN1, id_IN5}, {id_IN2, id_IN6}, {id_IN3, id_IN7}, {id_IN4, id_IN8},
};
static dict<IdString, IdString> map_both = {
{ id_D0_00, id_IN1},
{ id_D1_00, id_IN2},
{ id_D0_01, id_IN3},
{ id_D1_01, id_IN4},
{ id_D0_10, id_IN1},
{ id_D1_10, id_IN3},
{ id_D0_02, id_IN5},
{ id_D1_02, id_IN6},
{ id_D0_03, id_IN7},
{ id_D1_03, id_IN8},
{ id_D0_11, id_IN5},
{ id_D1_11, id_IN7},
static dict<IdString, IdString> map_both = {
{id_D0_00, id_IN1}, {id_D1_00, id_IN2}, {id_D0_01, id_IN3}, {id_D1_01, id_IN4},
{id_D0_10, id_IN1}, {id_D1_10, id_IN3}, {id_D0_02, id_IN5}, {id_D1_02, id_IN6},
{id_D0_03, id_IN7}, {id_D1_03, id_IN8}, {id_D0_11, id_IN5}, {id_D1_11, id_IN7},
};
int z = (cell->bel != BelId()) ? (ctx->getBelLocation(cell->bel).z % 2) : 0;
@ -149,14 +122,14 @@ bool GateMateImpl::getCellDelay(const CellInfo *cell, IdString fromPort, IdStrin
}
return get_delay_from_tmg_db(ctx->idf("timing__ARBLUT_%s_%s", fp.c_str(ctx), tp.c_str(ctx)), delay);
} else if (cell->type.in(id_CPE_ADDF, id_CPE_ADDF2)) {
IdString fp = fromPort, tp = toPort;
IdString fp = fromPort, tp = toPort;
if (map_both.count(fp))
fp = map_both[fp];
if (map_both.count(tp))
tp = map_both[tp];
return get_delay_from_tmg_db(ctx->idf("timing__ADDF2Y1_%s_%s", fp.c_str(ctx), tp.c_str(ctx)), delay);
} else if (cell->type.in(id_CPE_MX4)) {
IdString fp = fromPort, tp = toPort;
IdString fp = fromPort, tp = toPort;
if (map_both.count(fp))
fp = map_both[fp];
if (map_both.count(tp))
@ -226,29 +199,29 @@ TimingPortClass GateMateImpl::getPortTimingClass(const CellInfo *cell, IdString
auto disconnected = [cell](IdString p) { return !cell->ports.count(p) || cell->ports.at(p).net == nullptr; };
clockInfoCount = 0;
if (cell->type.in(id_CPE_L2T4, id_CPE_LT_L, id_CPE_LT_U)) {
if (port.in(id_IN1, id_IN2, id_IN3, id_IN4, id_COMBIN, id_CINY1, id_CINY2, id_CINX, id_PINX,
id_D0_00, id_D1_00, id_D0_01, id_D1_01, id_D0_10, id_D1_10,
id_D0_02, id_D1_02, id_D0_03, id_D1_03, id_D0_11, id_D1_11 ))
if (port.in(id_IN1, id_IN2, id_IN3, id_IN4, id_COMBIN, id_CINY1, id_CINY2, id_CINX, id_PINX, id_D0_00, id_D1_00,
id_D0_01, id_D1_01, id_D0_10, id_D1_10, id_D0_02, id_D1_02, id_D0_03, id_D1_03, id_D0_11, id_D1_11))
return TMG_COMB_INPUT;
if (port == id_OUT && disconnected(id_IN1) && disconnected(id_IN2) && disconnected(id_IN3) && disconnected(id_IN4) &&
disconnected(id_D0_00) && disconnected(id_D1_00) && disconnected(id_D0_01) && disconnected(id_D1_01) && disconnected(id_D0_10) && disconnected(id_D1_10) &&
disconnected(id_D0_02) && disconnected(id_D1_02) && disconnected(id_D0_03) && disconnected(id_D1_03) && disconnected(id_D0_11) && disconnected(id_D1_11))
if (port == id_OUT && disconnected(id_IN1) && disconnected(id_IN2) && disconnected(id_IN3) &&
disconnected(id_IN4) && disconnected(id_D0_00) && disconnected(id_D1_00) && disconnected(id_D0_01) &&
disconnected(id_D1_01) && disconnected(id_D0_10) && disconnected(id_D1_10) && disconnected(id_D0_02) &&
disconnected(id_D1_02) && disconnected(id_D0_03) && disconnected(id_D1_03) && disconnected(id_D0_11) &&
disconnected(id_D1_11))
return TMG_IGNORE; // LUT with no inputs is a constant
if (port.in(id_OUT))
return TMG_COMB_OUTPUT;
return TMG_IGNORE;
} else if (cell->type.in(id_CPE_ADDF, id_CPE_ADDF2)) {
if (port.in(id_IN1, id_IN2, id_IN3, id_IN4, id_IN5, id_IN6, id_IN7, id_IN8, id_CINX, id_CINY1,
id_D0_00, id_D1_00, id_D0_01, id_D1_01, id_D0_10, id_D1_10,
id_D0_02, id_D1_02, id_D0_03, id_D1_03, id_D0_11, id_D1_11 ))
if (port.in(id_IN1, id_IN2, id_IN3, id_IN4, id_IN5, id_IN6, id_IN7, id_IN8, id_CINX, id_CINY1, id_D0_00,
id_D1_00, id_D0_01, id_D1_01, id_D0_10, id_D1_10, id_D0_02, id_D1_02, id_D0_03, id_D1_03, id_D0_11,
id_D1_11))
return TMG_COMB_INPUT;
if (port.in(id_OUT1, id_OUT2, id_COUTY1))
return TMG_COMB_OUTPUT;
return TMG_IGNORE;
} else if (cell->type.in(id_CPE_MX4)) {
if (port.in(id_IN1, id_IN2, id_IN3, id_IN4, id_IN5, id_IN6, id_IN7, id_IN8,
id_D0_00, id_D1_00, id_D0_01, id_D1_01, id_D0_10, id_D1_10,
id_D0_02, id_D1_02, id_D0_03, id_D1_03, id_D0_11, id_D1_11 ))
if (port.in(id_IN1, id_IN2, id_IN3, id_IN4, id_IN5, id_IN6, id_IN7, id_IN8, id_D0_00, id_D1_00, id_D0_01,
id_D1_01, id_D0_10, id_D1_10, id_D0_02, id_D1_02, id_D0_03, id_D1_03, id_D0_11, id_D1_11))
return TMG_COMB_INPUT;
if (port.in(id_OUT1))
return TMG_COMB_OUTPUT;

205
himbaechel/uarch/gatemate/gatemate.cc
View File

@ -447,117 +447,76 @@ void GateMateImpl::postRoute()
}
}
log_info("Check CPEs..\n");
dict<IdString,int> cfg;
dict<IdString,IdString> port_mapping;
dict<IdString, int> cfg;
dict<IdString, IdString> port_mapping;
auto add_input = [&](IdString orig_port, IdString port, bool merged) {
static dict<IdString,IdString> convert_port = {
{ctx->id("CPE.IN1"),id_IN1},
{ctx->id("CPE.IN2"),id_IN2},
{ctx->id("CPE.IN3"),id_IN3},
{ctx->id("CPE.IN4"),id_IN4},
{ctx->id("CPE.IN5"),id_IN1},
{ctx->id("CPE.IN6"),id_IN2},
{ctx->id("CPE.IN7"),id_IN3},
{ctx->id("CPE.IN8"),id_IN4},
{ctx->id("CPE.PINY1"),id_PINY1},
{ctx->id("CPE.CINX"),id_CINX},
{ctx->id("CPE.PINX"),id_PINX}
};
static dict<IdString,IdString> convert_port_merged = {
{ctx->id("CPE.IN1"),id_IN1},
{ctx->id("CPE.IN2"),id_IN2},
{ctx->id("CPE.IN3"),id_IN3},
{ctx->id("CPE.IN4"),id_IN4},
{ctx->id("CPE.IN5"),id_IN5},
{ctx->id("CPE.IN6"),id_IN6},
{ctx->id("CPE.IN7"),id_IN7},
{ctx->id("CPE.IN8"),id_IN8},
{ctx->id("CPE.PINY1"),id_PINY1},
{ctx->id("CPE.CINX"),id_CINX},
{ctx->id("CPE.PINX"),id_PINX}
};
static dict<IdString, IdString> convert_port = {
{ctx->id("CPE.IN1"), id_IN1}, {ctx->id("CPE.IN2"), id_IN2}, {ctx->id("CPE.IN3"), id_IN3},
{ctx->id("CPE.IN4"), id_IN4}, {ctx->id("CPE.IN5"), id_IN1}, {ctx->id("CPE.IN6"), id_IN2},
{ctx->id("CPE.IN7"), id_IN3}, {ctx->id("CPE.IN8"), id_IN4}, {ctx->id("CPE.PINY1"), id_PINY1},
{ctx->id("CPE.CINX"), id_CINX}, {ctx->id("CPE.PINX"), id_PINX}};
static dict<IdString, IdString> convert_port_merged = {
{ctx->id("CPE.IN1"), id_IN1}, {ctx->id("CPE.IN2"), id_IN2}, {ctx->id("CPE.IN3"), id_IN3},
{ctx->id("CPE.IN4"), id_IN4}, {ctx->id("CPE.IN5"), id_IN5}, {ctx->id("CPE.IN6"), id_IN6},
{ctx->id("CPE.IN7"), id_IN7}, {ctx->id("CPE.IN8"), id_IN8}, {ctx->id("CPE.PINY1"), id_PINY1},
{ctx->id("CPE.CINX"), id_CINX}, {ctx->id("CPE.PINX"), id_PINX}};
if (convert_port.count(port)) {
//printf("CONVERTED %s %s\n",orig_port.c_str(ctx), port.c_str(ctx));
port_mapping.emplace(orig_port, merged ? convert_port_merged[port] : convert_port[port]);
};
};
auto check_input = [&](CellInfo *cell, IdString port, bool merged) {
if (cell->getPort(port)) {
NetInfo *net = cell->getPort(port);
WireId pin_wire = ctx->getBelPinWire(cell->bel, port);
if (net->wires.count(pin_wire)) {
//printf("Found pin connection\n");
auto &p = net->wires.at(pin_wire);
//printf("pip: %s -> %s \n",ctx->getPipName(p.pip)[1].c_str(ctx), ctx->getPipName(p.pip)[2].c_str(ctx));
WireId src = ctx->getPipSrcWire(p.pip);
const auto &extra_data = *pip_extra_data(p.pip);
if (extra_data.type == PipExtra::PIP_EXTRA_MUX) {
//printf("name:%s %d\n",IdString(extra_data.name).c_str(ctx),extra_data.value);
cfg.emplace(IdString(extra_data.name),extra_data.value);
cfg.emplace(IdString(extra_data.name), extra_data.value);
add_input(port, ctx->getWireName(src)[1], merged);
}
if (net->wires.count(src)) {
//printf("Found pin connection\n");
auto &p = net->wires.at(src);
//printf("pip: %s -> %s \n",ctx->getPipName(p.pip)[1].c_str(ctx), ctx->getPipName(p.pip)[2].c_str(ctx));
WireId src = ctx->getPipSrcWire(p.pip);
//printf("wire : %s\n",ctx->getWireName(src)[1].c_str(ctx));
const auto &extra_data = *pip_extra_data(p.pip);
if (extra_data.type == PipExtra::PIP_EXTRA_MUX) {
//printf("name:%s %d\n",IdString(extra_data.name).c_str(ctx),extra_data.value);
cfg.emplace(IdString(extra_data.name),extra_data.value);
cfg.emplace(IdString(extra_data.name), extra_data.value);
add_input(port, ctx->getWireName(src)[1], merged);
}
if (net->wires.count(src)) {
//printf("Found pin connection\n");
auto &p = net->wires.at(src);
//printf("pip: %s -> %s \n",ctx->getPipName(p.pip)[1].c_str(ctx), ctx->getPipName(p.pip)[2].c_str(ctx));
WireId src = ctx->getPipSrcWire(p.pip);
//printf("wire : %s\n",ctx->getWireName(src)[1].c_str(ctx));
const auto &extra_data = *pip_extra_data(p.pip);
if (extra_data.type == PipExtra::PIP_EXTRA_MUX) {
//printf("name:%s %d\n",IdString(extra_data.name).c_str(ctx),extra_data.value);
cfg.emplace(IdString(extra_data.name),extra_data.value);
cfg.emplace(IdString(extra_data.name), extra_data.value);
add_input(port, ctx->getWireName(src)[1], merged);
}
} else {
//printf("No pin connection\n");
}
} else {
//printf("No pin connection\n");
}
} else {
//printf("No pin connection\n");
}
}
};
auto swap_lut2_inputs = [&](int lut) -> int {
// bit permutation: [3,1,2,0]
return ((lut & 0b1000)) | // b3 -> bit 3
((lut & 0b0010) << 1) | // b1 -> bit 2
((lut & 0b0100) >> 1) | // b2 -> bit 1
((lut & 0b0001)); // b0 -> bit 0
return ((lut & 0b1000)) | // b3 -> bit 3
((lut & 0b0010) << 1) | // b1 -> bit 2
((lut & 0b0100) >> 1) | // b2 -> bit 1
((lut & 0b0001)); // b0 -> bit 0
};
for (auto &cell : ctx->cells) {
if (cell.second->type.in(id_CPE_L2T4)) {
//printf("\n");
cfg.clear();
port_mapping.clear();
//printf("type:%s name:%s\n",cell.second->type.c_str(ctx),cell.second->name.c_str(ctx));
int l00 = int_or_default(cell.second->params, id_INIT_L00, 0);
int l01 = int_or_default(cell.second->params, id_INIT_L01, 0);
int l10 = int_or_default(cell.second->params, id_INIT_L10, 0);
//printf("L00 %04b\n",l00);
//printf("L01 %04b\n",l01);
//printf("L10 %04b\n",l10);
check_input(cell.second.get(), id_D0_00, false);
check_input(cell.second.get(), id_D1_00, false);
check_input(cell.second.get(), id_D0_01, false);
@ -565,116 +524,96 @@ void GateMateImpl::postRoute()
check_input(cell.second.get(), id_D0_10, false);
check_input(cell.second.get(), id_D1_10, false);
if (cfg.count(ctx->id("LUT2_11")) || cfg.count(ctx->id("LUT2_10"))) {
//printf("LUT2 like\n");
if (cfg.count(ctx->id("LUT2_11"))) { //lower
if (cfg.count(ctx->id("LUT2_11"))) { // lower
if (cfg.count(ctx->id("LUT2_02")) && !cfg.count(ctx->id("LUT2_03"))) {
// both inputs on 02
l00 = l10; // config is now in 02
l00 = l10; // config is now in 02
l10 = 0b1010; // LUT_D0 - we propagate only
} else if (!cfg.count(ctx->id("LUT2_02")) && cfg.count(ctx->id("LUT2_03"))) {
// both inputs on 03
l01 = l10; // config is now in 03
l01 = l10; // config is now in 03
l10 = 0b1010; // LUT_D0 - we propagate only
} else {
// one input on 02, other on 03 (or LUT1)
if (cfg.count(ctx->id("LUT2_02"))) {
if (cfg.count(ctx->id("LUT2_02")))
l00 = 0b1010; // LUT_D0 - we propagate only
}
if (cfg.count(ctx->id("LUT2_03"))) {
if (cfg.count(ctx->id("LUT2_03")))
l01 = 0b1010; // LUT_D0 - we propagate only
}
}
if (cfg.at(ctx->id("LUT2_11"))==1)
if (cfg.at(ctx->id("LUT2_11")) == 1)
l10 = swap_lut2_inputs(l10);
if (cfg.count(ctx->id("LUT2_02")) && (cfg.at(ctx->id("LUT2_02"))==1))
if (cfg.count(ctx->id("LUT2_02")) && (cfg.at(ctx->id("LUT2_02")) == 1))
l00 = swap_lut2_inputs(l00);
if (cfg.count(ctx->id("LUT2_03")) && (cfg.at(ctx->id("LUT2_03"))==1))
if (cfg.count(ctx->id("LUT2_03")) && (cfg.at(ctx->id("LUT2_03")) == 1))
l01 = swap_lut2_inputs(l01);
} else { // upper part
if (cfg.count(ctx->id("LUT2_00")) && !cfg.count(ctx->id("LUT2_01"))) {
// both inputs on 02
l00 = l10; // config is now in 02
l00 = l10; // config is now in 02
l10 = 0b1010; // LUT_D0 - we propagate only
} else if (!cfg.count(ctx->id("LUT2_00")) && cfg.count(ctx->id("LUT2_01"))) {
// both inputs on 03
l01 = l10; // config is now in 03
l01 = l10; // config is now in 03
l10 = 0b1010; // LUT_D0 - we propagate only
} else {
// one input on 02, other on 03 (or LUT1)
if (cfg.count(ctx->id("LUT2_00"))) {
if (cfg.count(ctx->id("LUT2_00")))
l00 = 0b1010; // LUT_D0 - we propagate only
}
if (cfg.count(ctx->id("LUT2_01"))) {
if (cfg.count(ctx->id("LUT2_01")))
l01 = 0b1010; // LUT_D0 - we propagate only
}
}
if (cfg.at(ctx->id("LUT2_10"))==1)
if (cfg.at(ctx->id("LUT2_10")) == 1)
l10 = swap_lut2_inputs(l10);
if (cfg.count(ctx->id("LUT2_00")) && (cfg.at(ctx->id("LUT2_00"))==1))
if (cfg.count(ctx->id("LUT2_00")) && (cfg.at(ctx->id("LUT2_00")) == 1))
l00 = swap_lut2_inputs(l00);
if (cfg.count(ctx->id("LUT2_01")) && (cfg.at(ctx->id("LUT2_01"))==1))
if (cfg.count(ctx->id("LUT2_01")) && (cfg.at(ctx->id("LUT2_01")) == 1))
l01 = swap_lut2_inputs(l01);
}
//printf("updated\n=========\n");
//printf("L00 %04b\n",l00);
//printf("L01 %04b\n",l01);
//printf("L10 %04b\n",l10);
cell.second->params[id_INIT_L00] = Property(l00,4);
cell.second->params[id_INIT_L01] = Property(l01,4);
cell.second->params[id_INIT_L10] = Property(l10,4);
cell.second->params[id_INIT_L00] = Property(l00, 4);
cell.second->params[id_INIT_L01] = Property(l01, 4);
cell.second->params[id_INIT_L10] = Property(l10, 4);
cell.second->renamePort(id_D0_10, port_mapping[id_D0_10]);
cell.second->renamePort(id_D1_10, port_mapping[id_D1_10]);
} else {
if (cfg.count(ctx->id("LUT2_00")) && cfg.at(ctx->id("LUT2_00"))==1) {
if (cfg.count(ctx->id("LUT2_00")) && cfg.at(ctx->id("LUT2_00")) == 1)
l00 = swap_lut2_inputs(l00);
}
if (cfg.count(ctx->id("LUT2_01")) && cfg.at(ctx->id("LUT2_01"))==1) {
if (cfg.count(ctx->id("LUT2_01")) && cfg.at(ctx->id("LUT2_01")) == 1)
l01 = swap_lut2_inputs(l01);
}
if (cfg.count(ctx->id("LUT2_02")) && cfg.at(ctx->id("LUT2_02"))==1) {
if (cfg.count(ctx->id("LUT2_02")) && cfg.at(ctx->id("LUT2_02")) == 1)
l00 = swap_lut2_inputs(l00);
}
if (cfg.count(ctx->id("LUT2_03")) && cfg.at(ctx->id("LUT2_03"))==1) {
if (cfg.count(ctx->id("LUT2_03")) && cfg.at(ctx->id("LUT2_03")) == 1)
l01 = swap_lut2_inputs(l01);
}
cell.second->params[id_INIT_L00] = Property(l00,4);
cell.second->params[id_INIT_L01] = Property(l01,4);
cell.second->params[id_INIT_L10] = Property(l10,4);
cell.second->params[id_INIT_L00] = Property(l00, 4);
cell.second->params[id_INIT_L01] = Property(l01, 4);
cell.second->params[id_INIT_L10] = Property(l10, 4);
cell.second->renamePort(id_D0_00, port_mapping[id_D0_00]);
cell.second->renamePort(id_D1_00, port_mapping[id_D1_00]);
cell.second->renamePort(id_D0_01, port_mapping[id_D0_01]);
cell.second->renamePort(id_D1_01, port_mapping[id_D1_01]);
cell.second->renamePort(id_D1_01, port_mapping[id_D1_01]);
}
if (cfg.count(ctx->id("CPE.C_I1")))
cell.second->params[id_C_I1] = Property(1,1);
if (cfg.count(ctx->id("CPE.C_I2")))
cell.second->params[id_C_I2] = Property(1,1);
if (cfg.count(ctx->id("CPE.C_I3")))
cell.second->params[id_C_I3] = Property(1,1);
if (cfg.count(ctx->id("CPE.C_I4")))
cell.second->params[id_C_I4] = Property(1,1);
if (cfg.count(ctx->id("CPE.C_I1")))
cell.second->params[id_C_I1] = Property(1, 1);
if (cfg.count(ctx->id("CPE.C_I2")))
cell.second->params[id_C_I2] = Property(1, 1);
if (cfg.count(ctx->id("CPE.C_I3")))
cell.second->params[id_C_I3] = Property(1, 1);
if (cfg.count(ctx->id("CPE.C_I4")))
cell.second->params[id_C_I4] = Property(1, 1);
}
if (cell.second->type.in(id_CPE_MX4, id_CPE_ADDF, id_CPE_ADDF2)) {
//printf("\n");
cfg.clear();
port_mapping.clear();
//printf("type:%s name:%s\n",cell.second->type.c_str(ctx),cell.second->name.c_str(ctx));
int l00 = int_or_default(cell.second->params, id_INIT_L00, 0);
int l01 = int_or_default(cell.second->params, id_INIT_L01, 0);
//int l10 = int_or_default(cell.second->params, id_INIT_L10, 0);
int l02 = int_or_default(cell.second->params, id_INIT_L02, 0);
int l03 = int_or_default(cell.second->params, id_INIT_L03, 0);
//int l11 = int_or_default(cell.second->params, id_INIT_L11, 0);
//printf("L00 %04b\n",l00);
//printf("L01 %04b\n",l01);
//printf("L10 %04b\n",l10);
check_input(cell.second.get(), id_D0_00, true);
check_input(cell.second.get(), id_D1_00, true);
check_input(cell.second.get(), id_D0_01, true);
@ -684,31 +623,19 @@ void GateMateImpl::postRoute()
check_input(cell.second.get(), id_D0_03, true);
check_input(cell.second.get(), id_D1_03, true);
//check_input(cell.second.get(), id_D0_10);
//check_input(cell.second.get(), id_D1_10);
//check_input(cell.second.get(), id_D0_11);
//check_input(cell.second.get(), id_D1_11);
if (cfg.count(ctx->id("LUT2_00")) && cfg.at(ctx->id("LUT2_00"))==1) {
if (cfg.count(ctx->id("LUT2_00")) && cfg.at(ctx->id("LUT2_00")) == 1)
l00 = swap_lut2_inputs(l00);
}
if (cfg.count(ctx->id("LUT2_01")) && cfg.at(ctx->id("LUT2_01"))==1) {
if (cfg.count(ctx->id("LUT2_01")) && cfg.at(ctx->id("LUT2_01")) == 1)
l01 = swap_lut2_inputs(l01);
}
if (cfg.count(ctx->id("LUT2_02")) && cfg.at(ctx->id("LUT2_02"))==1) {
if (cfg.count(ctx->id("LUT2_02")) && cfg.at(ctx->id("LUT2_02")) == 1)
l02 = swap_lut2_inputs(l02);
}
if (cfg.count(ctx->id("LUT2_03")) && cfg.at(ctx->id("LUT2_03"))==1) {
if (cfg.count(ctx->id("LUT2_03")) && cfg.at(ctx->id("LUT2_03")) == 1)
l03 = swap_lut2_inputs(l03);
}
cell.second->params[id_INIT_L00] = Property(l00,4);
cell.second->params[id_INIT_L01] = Property(l01,4);
cell.second->params[id_INIT_L02] = Property(l02,4);
cell.second->params[id_INIT_L03] = Property(l03,4);
//cell.second->params[id_INIT_L10] = Property(l10,4);
//cell.second->params[id_INIT_L11] = Property(l11,4);
cell.second->params[id_INIT_L00] = Property(l00, 4);
cell.second->params[id_INIT_L01] = Property(l01, 4);
cell.second->params[id_INIT_L02] = Property(l02, 4);
cell.second->params[id_INIT_L03] = Property(l03, 4);
cell.second->renamePort(id_D0_00, port_mapping[id_D0_00]);
cell.second->renamePort(id_D1_00, port_mapping[id_D1_00]);

77
himbaechel/uarch/gatemate/pack.cc
View File

@ -145,31 +145,69 @@ inline int lut2_apply_constant_inputs(int init, int d0_const, int d1_const)
int D0 = (i >> 0) & 1;
// Apply constants if present
if (d0_const != -1) D0 = d0_const;
if (d1_const != -1) D1 = d1_const;
if (d0_const != -1)
D0 = d0_const;
if (d1_const != -1)
D1 = d1_const;
int src = (D1 << 1) | D0;
out[i] =
(src == 0) ? b0 :
(src == 1) ? b1 :
(src == 2) ? b2 :
b3;
out[i] = (src == 0) ? b0 : (src == 1) ? b1 : (src == 2) ? b2 : b3;
}
return (out[3] << 3) | (out[2] << 2) | (out[1] << 1) | out[0];
}
void GateMatePacker::optimize_lut()
void GateMatePacker::optimize_lut2(CellInfo &ci, IdString i0, IdString i1, IdString init)
{
auto lut2_same_inputs = [&](int lut) -> int {
int b0 = lut & 1; // bit 0
int b3 = (lut >> 3) & 1; // bit 3
int b0 = lut & 1; // bit 0
int b3 = (lut >> 3) & 1; // bit 3
return (b3 << 3) | (b3 << 2) | (b0 << 1) | b0;
};
uint8_t val = int_or_default(ci.params, init, 0);
int d0_const = -1;
int d1_const = -1;
if (ci.getPort(i0) && ci.getPort(i0) == net_PACKER_GND) {
d0_const = 0;
ci.disconnectPort(i0);
}
if (ci.getPort(i0) && ci.getPort(i0) == net_PACKER_VCC) {
d0_const = 1;
ci.disconnectPort(i0);
}
if (ci.getPort(i1) && ci.getPort(i1) == net_PACKER_GND) {
d1_const = 0;
ci.disconnectPort(i1);
}
if (ci.getPort(i1) && ci.getPort(i1) == net_PACKER_VCC) {
d1_const = 1;
ci.disconnectPort(i1);
}
val = lut2_apply_constant_inputs(val, d0_const, d1_const);
if (ci.getPort(i0) == ci.getPort(i1)) {
val = lut2_same_inputs(val);
ci.params[init] = Property(val, 4);
ci.disconnectPort(i1);
}
}
void GateMatePacker::optimize_lut()
{
for (auto &cell : ctx->cells) {
CellInfo &ci = *cell.second;
if (ci.type == id_CC_LUT2) {
optimize_lut2(ci, id_I0, id_I1, id_INIT);
} else if (ci.type == id_CC_L2T4) {
optimize_lut2(ci, id_I0, id_I1, id_INIT_L00);
optimize_lut2(ci, id_I2, id_I3, id_INIT_L01);
} else if (ci.type == id_CC_L2T5) {
optimize_lut2(ci, id_I0, id_I1, id_INIT_L02);
optimize_lut2(ci, id_I2, id_I3, id_INIT_L03);
}
if (!ci.type.in(id_CC_LUT1, id_CC_LUT2))
continue;
if (ci.attrs.count(ctx->id("keep")))
@ -183,23 +221,6 @@ void GateMatePacker::optimize_lut()
uint8_t val = int_or_default(ci.params, id_INIT, 0);
if (ci.type == id_CC_LUT1)
val = val << 2 | val;
else {
int d0_const = -1;
int d1_const = -1;
if (ci.getPort(id_I0) && ci.getPort(id_I0)==net_PACKER_GND) { d0_const = 0; ci.disconnectPort(id_I0); }
if (ci.getPort(id_I0) && ci.getPort(id_I0)==net_PACKER_VCC) { d0_const = 1; ci.disconnectPort(id_I0); }
if (ci.getPort(id_I1) && ci.getPort(id_I1)==net_PACKER_GND) { d1_const = 0; ci.disconnectPort(id_I1); }
if (ci.getPort(id_I1) && ci.getPort(id_I1)==net_PACKER_VCC) { d1_const = 1; ci.disconnectPort(id_I1); }
val = lut2_apply_constant_inputs(val, d0_const, d1_const);
if (ci.getPort(id_I0)==ci.getPort(id_I1)) {
printf("LUT2 with same inputs %s\n",ci.name.c_str(ctx));
val = lut2_same_inputs(val);
ci.params[id_INIT] = Property(val,4);
ci.disconnectPort(id_I1);
}
}
switch (val) {
case LUT_ZERO: // constant 0
move_connections(o_net, net_PACKER_GND);
@ -361,7 +382,6 @@ void GateMatePacker::repack_cpe()
if (!cell.second->params.count(id_INIT_L20))
cell.second->params[id_INIT_L20] = Property(LUT_D1, 4);
if (cell.second->getPort(id_D0_10)) {
}
}
cell.second->params[id_L2T4_UPPER] = Property((l.z == CPE_LT_U_Z) ? 1 : 0, 1);
@ -380,7 +400,6 @@ void GateMatePacker::repack_cpe()
cell.second->renamePort(id_D0_10, id_D0_11);
cell.second->renamePort(id_D1_10, id_D1_11);
cell.second->renamePort(id_IN1, id_IN5);
cell.second->renamePort(id_IN2, id_IN6);
cell.second->renamePort(id_IN3, id_IN7);

1
himbaechel/uarch/gatemate/pack.h
View File

@ -85,6 +85,7 @@ struct GateMatePacker
void disconnect_not_used();
void optimize_lut();
void optimize_lut2(CellInfo &ci, IdString i0, IdString i1, IdString init);
void optimize_mx();
void optimize_ff();
void count_cell(CellInfo &ci);

8
himbaechel/uarch/gatemate/pack_cpe.cc
View File

@ -238,15 +238,14 @@ void GateMatePacker::pack_cpe()
if (ci.type == id_CC_LUT1)
val = val << 2 | val;
ci.params[id_INIT_L10] = Property(val, 4);
//ci.params[id_INIT_L00] = Property(val, 4);
// ci.params[id_INIT_L00] = Property(val, 4);
ci.unsetParam(id_INIT);
//ci.params[id_INIT_L10] = Property(LUT_D0, 4);
// ci.params[id_INIT_L10] = Property(LUT_D0, 4);
} else {
ci.renamePort(id_I0, id_D0_00);
ci.renamePort(id_I1, id_D1_00);
ci.renamePort(id_I2, id_D0_01);
ci.renamePort(id_I3, id_D1_01);
}
ci.type = id_CPE_L2T4;
}
@ -303,7 +302,7 @@ void GateMatePacker::pack_cpe()
upper->constr_abs_z = true;
upper->constr_z = CPE_LT_U_Z;
ci->movePortTo(id_I4, upper, id_D0_10);
//upper->params[id_INIT_L00] = Property(LUT_D0, 4);
// upper->params[id_INIT_L00] = Property(LUT_D0, 4);
upper->params[id_INIT_L10] = Property(LUT_D0, 4);
ci->constr_children.push_back(upper);
@ -817,7 +816,6 @@ std::pair<CellInfo *, CellInfo *> GateMatePacker::move_ram_o(CellInfo *cell, IdS
cpe_half->params[id_INIT_L10] = Property(LUT_D0, 4);
cell->movePortTo(origPort, cpe_half, id_D0_10);
}
cpe_ramio->params[id_C_RAM_O] = Property(1, 1);
NetInfo *ram_o = ctx->createNet(ctx->idf("%s$ram_o", cpe_half->name.c_str(ctx)));