mirror of https://github.com/YosysHQ/nextpnr.git
Merge 32b1d1648a into 2a8bab976d
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commit
e552b0010a
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@ -341,14 +341,25 @@ struct BitstreamBackend
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if (l.z == CPE_LT_FULL_Z) {
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if (!cell.second->type.in(id_CPE_MULT)) {
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if (cell.second->type.in(id_CPE_MX4)) {
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update_cpe_mux(cell.second.get(), id_IN1, id_INIT_L11, 0, params);
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update_cpe_mux(cell.second.get(), id_IN2, id_INIT_L11, 1, params);
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update_cpe_mux(cell.second.get(), id_IN3, id_INIT_L11, 2, params);
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update_cpe_mux(cell.second.get(), id_IN4, id_INIT_L11, 3, params);
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update_cpe_lt(cell.second.get(), id_IN5, id_INIT_L02, params, true);
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update_cpe_lt(cell.second.get(), c_i3 ? id_PINY1 : id_IN6, id_INIT_L02, params, false);
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update_cpe_lt(cell.second.get(), id_IN7, id_INIT_L03, params, true);
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update_cpe_lt(cell.second.get(), c_i4 ? id_PINX : id_IN8, id_INIT_L03, params, false);
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if (int_or_default(params, id_INIT_L20, 0) == LUT_D0) {
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update_cpe_lt(cell.second.get(), id_IN1, id_INIT_L00, params, true);
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update_cpe_lt(cell.second.get(), c_i1 ? id_PINY1 : id_IN2, id_INIT_L00, params, false);
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update_cpe_lt(cell.second.get(), id_IN3, id_INIT_L01, params, true);
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update_cpe_lt(cell.second.get(), c_i2 ? id_CINX : id_IN4, id_INIT_L01, params, false);
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update_cpe_mux(cell.second.get(), id_IN5, id_INIT_L10, 0, params);
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update_cpe_mux(cell.second.get(), id_IN6, id_INIT_L10, 1, params);
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update_cpe_mux(cell.second.get(), id_IN7, id_INIT_L10, 2, params);
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update_cpe_mux(cell.second.get(), id_IN8, id_INIT_L10, 3, params);
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} else {
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update_cpe_mux(cell.second.get(), id_IN1, id_INIT_L11, 0, params);
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update_cpe_mux(cell.second.get(), id_IN2, id_INIT_L11, 1, params);
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update_cpe_mux(cell.second.get(), id_IN3, id_INIT_L11, 2, params);
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update_cpe_mux(cell.second.get(), id_IN4, id_INIT_L11, 3, params);
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update_cpe_lt(cell.second.get(), id_IN5, id_INIT_L02, params, true);
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update_cpe_lt(cell.second.get(), c_i3 ? id_PINY1 : id_IN6, id_INIT_L02, params, false);
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update_cpe_lt(cell.second.get(), id_IN7, id_INIT_L03, params, true);
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update_cpe_lt(cell.second.get(), c_i4 ? id_PINX : id_IN8, id_INIT_L03, params, false);
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}
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} else {
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update_cpe_lt(cell.second.get(), id_IN1, id_INIT_L00, params, true);
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update_cpe_lt(cell.second.get(), c_i1 ? id_PINY1 : id_IN2, id_INIT_L00, params, false);
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@ -322,9 +322,6 @@ void GateMatePacker::pack_cpe()
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ci.cluster = ci.name;
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ci.renamePort(id_Y, id_OUT);
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ci.renamePort(id_S0, id_D0_00); // IN5
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ci.renamePort(id_S1, id_D0_01); // IN7
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uint8_t select = 0;
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uint8_t invert = 0;
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for (int i = 0; i < 4; i++) {
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@ -340,26 +337,52 @@ void GateMatePacker::pack_cpe()
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}
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}
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}
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ci.params[id_C_FUNCTION] = Property(C_MX4, 3);
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ci.params[id_INIT_L02] = Property(LUT_D0, 4); // IN5
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ci.params[id_INIT_L03] = Property(LUT_D0, 4); // IN7
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ci.params[id_INIT_L11] = Property(invert, 4); // Inversion bits
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ci.params[id_INIT_L20] = Property(LUT_D1, 4); // Always D1
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ci.type = id_CPE_LT_L;
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if (0) {
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ci.params[id_C_FUNCTION] = Property(C_MX4, 3);
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ci.params[id_INIT_L02] = Property(LUT_D0, 4); // IN5
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ci.params[id_INIT_L03] = Property(LUT_D0, 4); // IN7
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ci.params[id_INIT_L11] = Property(invert, 4); // Inversion bits
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ci.params[id_INIT_L20] = Property(LUT_D1, 4); // Always D1
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ci.type = id_CPE_LT_L;
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ci.renamePort(id_S0, id_D0_00); // IN5
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ci.renamePort(id_S1, id_D0_01); // IN7
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CellInfo *upper = create_cell_ptr(id_CPE_LT_U, ctx->idf("%s$upper", ci.name.c_str(ctx)));
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upper->cluster = ci.name;
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upper->region = ci.region;
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upper->constr_abs_z = false;
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upper->constr_z = -1;
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upper->params[id_INIT_L10] = Property(select, 4); // Selection bits
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upper->params[id_C_FUNCTION] = Property(C_MX4, 3);
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CellInfo *upper = create_cell_ptr(id_CPE_LT_U, ctx->idf("%s$upper", ci.name.c_str(ctx)));
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upper->cluster = ci.name;
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upper->region = ci.region;
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upper->constr_abs_z = false;
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upper->constr_z = -1;
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upper->params[id_INIT_L10] = Property(select, 4); // Selection bits
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upper->params[id_C_FUNCTION] = Property(C_MX4, 3);
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ci.movePortTo(id_D0, upper, id_IN1);
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ci.movePortTo(id_D1, upper, id_IN2);
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ci.movePortTo(id_D2, upper, id_IN3);
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ci.movePortTo(id_D3, upper, id_IN4);
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ci.constr_children.push_back(upper);
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ci.movePortTo(id_D0, upper, id_IN1);
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ci.movePortTo(id_D1, upper, id_IN2);
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ci.movePortTo(id_D2, upper, id_IN3);
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ci.movePortTo(id_D3, upper, id_IN4);
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ci.constr_children.push_back(upper);
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} else {
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ci.params[id_C_FUNCTION] = Property(C_MX4, 3);
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ci.params[id_INIT_L11] = Property(select, 4); // Selection bits
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ci.params[id_INIT_L20] = Property(LUT_D0, 4); // Always D0
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ci.type = id_CPE_LT_L;
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ci.renamePort(id_D0, id_IN1);
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ci.renamePort(id_D1, id_IN2);
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ci.renamePort(id_D2, id_IN3);
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ci.renamePort(id_D3, id_IN4);
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CellInfo *upper = create_cell_ptr(id_CPE_LT_U, ctx->idf("%s$upper", ci.name.c_str(ctx)));
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upper->cluster = ci.name;
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upper->region = ci.region;
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upper->constr_abs_z = false;
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upper->constr_z = -1;
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upper->params[id_INIT_L00] = Property(LUT_D0, 4); // IN1
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upper->params[id_INIT_L01] = Property(LUT_D0, 4); // IN3
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upper->params[id_INIT_L10] = Property(invert, 4); // Inversion bits
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upper->params[id_C_FUNCTION] = Property(C_MX4, 3);
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ci.movePortTo(id_S0, upper, id_D0_00); // IN1
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ci.movePortTo(id_S1, upper, id_D0_01); // IN3
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ci.constr_children.push_back(upper);
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}
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NetInfo *o = ci.getPort(id_OUT);
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if (o) {
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