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Fix clock router and timings

This commit is contained in:
Miodrag Milanovic 2025-12-24 16:48:34 +01:00
parent 053a6d5cdb
commit dd0aca6578
2 changed files with 3 additions and 3 deletions
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4
himbaechel/uarch/gatemate/delay.cc
View File

@ -243,7 +243,7 @@ TimingPortClass GateMateImpl::getPortTimingClass(const CellInfo *cell, IdString
return TMG_COMB_OUTPUT;
return TMG_COMB_INPUT;
} else if (cell->type.in(id_CPE_FF, id_CPE_FF_L, id_CPE_FF_U, id_CPE_LATCH)) {
if (port == id_CLK)
if (port.in(id_CLK_INT))
return TMG_CLOCK_INPUT;
clockInfoCount = 1;
if (port == id_DOUT)
@ -364,7 +364,7 @@ TimingClockingInfo GateMateImpl::getPortClockingInfo(const CellInfo *cell, IdStr
if (cell->type.in(id_CPE_FF, id_CPE_FF_L, id_CPE_FF_U, id_CPE_LATCH)) {
bool inverted = int_or_default(cell->params, id_C_CPE_CLK, 0) == 0b01;
info.edge = inverted ? FALLING_EDGE : RISING_EDGE;
info.clock_port = id_CLK;
info.clock_port = id_CLK_INT;
if (port.in(id_DIN, id_EN, id_SR))
get_setuphold_from_tmg_db(id_timing_del_Setup_D_L, id_timing_del_Hold_D_L, info.setup, info.hold);
if (port.in(id_DOUT)) {

2
himbaechel/uarch/gatemate/route_clock.cc
View File

@ -52,7 +52,7 @@ void GateMateImpl::route_clock()
auto reserved_wires = dict<WireId, IdString>{};
auto feeds_clk_port = [&](PortRef &port) {
return (ctx->getBelBucketForCellType(port.cell->type) == id_CPE_FF) && port.port.in(id_CLK);
return (ctx->getBelBucketForCellType(port.cell->type) == id_CPE_FF) && port.port.in(id_CLK_INT);
};
auto feeds_ddr_port = [&](NetInfo *net, PortRef &port) {