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GOWIN. BUGFIX. BSRAM port renaming. (#1669) 

* GOWIN. BUGFIX. BSRAM port renaming.

The renumbering of the BSRAM pins has been corrected.

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>

* GOWIN. Comment BSRAM port renaming

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>

---------

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
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YRabbit 2026-03-15 06:52:05 +10:00 committed by GitHub
parent 2c16785078
commit cd36c9f0d5
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1 changed files with 5 additions and 1 deletions
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6
himbaechel/uarch/gowin/pack_bsram.cc
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@ -17,11 +17,15 @@ NEXTPNR_NAMESPACE_BEGIN
// =================================== // ===================================
// Block RAM // Block RAM
// =================================== // ===================================
// Memory is always 36-bit, consisting of 9-bit bytes; 8-bit primitives are
// formed by “skipping” every 9th bit on the DI and DO buses. Here, the
// skipping works as follows: if the primitive is 8-bit (16 or 32), then every
// 9th bit becomes the 10th bit and so on.
void GowinPacker::bsram_rename_ports(CellInfo *ci, int bit_width, char const *from, char const *to, int offset) void GowinPacker::bsram_rename_ports(CellInfo *ci, int bit_width, char const *from, char const *to, int offset)
{ {
int num = (bit_width == 9 || bit_width == 18 || bit_width == 36) ? 36 : 32; int num = (bit_width == 9 || bit_width == 18 || bit_width == 36) ? 36 : 32;
for (int i = 0, j = offset; i < num; ++i, ++j) { for (int i = 0, j = offset; i < num; ++i, ++j) {
if (((i + 1) % 9) == 0 && (bit_width == 16 || bit_width == 32)) { if (i && (i % 8) == 0 && (bit_width == 16 || bit_width == 32)) {
++j; ++j;
} }
ci->renamePort(ctx->idf(from, i), ctx->idf(to, offset ? j % 36 : j)); ci->renamePort(ctx->idf(from, i), ctx->idf(to, offset ? j % 36 : j));