gowin: exclude latch gate signals from clock buffer promotion

Latch cells are mapped to DFFs with a LATCH attribute, so their gate
signal drives the CLK port. This caused pack_buffered_nets to promote
the gate signal onto a global clock buffer (BUFG), which has different
timing/initialization behavior and caused the first gate transition
to be lost. Skip CLK pins on cells with the LATCH attribute when
checking for clock users.

himbaechel/uarch/gowin/pack.cc

@@ -334,6 +334,9 @@ void GowinPacker::pack_buffered_nets(void)
             bool has_clock_users = false;
             for (auto usr : ni->users) {
                 if (usr.port.in(id_CLKIN, id_CLK, id_CLK0, id_CLK1, id_CLK2, id_CLK3, id_CLKFB)) {
+                    // Latch gate signals drive CLK pins but are not clocks
+                    if (usr.port == id_CLK && usr.cell->attrs.count(id_LATCH))
+                        continue;
                     has_clock_users = true;
                     break;
                 }