mirror of https://github.com/YosysHQ/nextpnr.git
Make it more as in PR #1513
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@ -326,11 +326,9 @@ void GateMatePacker::pack_io_sel()
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cells.push_back(&ci);
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}
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std::vector<std::array<std::pair<CellInfo*,CellInfo*>, 9>> ddr(uarch->dies); // for each bank
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for (int i = 0; i < uarch->dies; ++i)
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for (int j = 0; j < 9; ++j)
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ddr[i][j] = {nullptr, nullptr};
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std::vector<std::array<std::pair<CellInfo *, CellInfo *>, 9>> ddr(
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uarch->dies, std::array<std::pair<CellInfo *, CellInfo *>, 9>{}
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);
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auto set_out_clk = [&](CellInfo *cell, CellInfo *target) -> bool {
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NetInfo *clk_net = cell->getPort(id_CLK);
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if (clk_net) {
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