mirror of https://github.com/YosysHQ/nextpnr.git
mux bridges need cell bel pins too
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parent
3227e4d717
commit
c03dfdc7dc
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@ -422,10 +422,16 @@ void GateMateImpl::reassign_bridges(NetInfo *ni, const dict<WireId, PipMap> &net
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NetInfo *new_net = ctx->createNet(ctx->idf("%s$muxout", name.c_str(ctx)));
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NetInfo *new_net = ctx->createNet(ctx->idf("%s$muxout", name.c_str(ctx)));
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IdString in_port = ctx->idf("IN%d", extra_data.value + 1);
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IdString in_port = ctx->idf("IN%d", extra_data.value + 1);
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cell->addInput(in_port);
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auto add_port = [&](const IdString id, PortType dir) {
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cell->connectPort(in_port, ni);
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cell->ports[id].name = id;
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cell->ports[id].type = dir;
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cell->cell_bel_pins[id] = std::vector{id};
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};
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cell->addOutput(id_MUXOUT);
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add_port(in_port, PORT_IN);
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add_port(id_MUXOUT, PORT_OUT);
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cell->connectPort(in_port, ni);
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cell->connectPort(id_MUXOUT, new_net);
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cell->connectPort(id_MUXOUT, new_net);
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num++;
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num++;
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@ -471,6 +477,7 @@ void GateMateImpl::reassign_cplines(NetInfo *ni, const dict<WireId, PipMap> &net
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auto add_port = [&](const IdString id, PortType dir) {
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auto add_port = [&](const IdString id, PortType dir) {
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cell->ports[id].name = id;
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cell->ports[id].name = id;
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cell->ports[id].type = dir;
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cell->ports[id].type = dir;
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cell->cell_bel_pins[id] = std::vector{id};
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};
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};
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add_port(id_OUT1, PORT_IN);
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add_port(id_OUT1, PORT_IN);
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@ -525,8 +532,6 @@ void GateMateImpl::reassign_cplines(NetInfo *ni, const dict<WireId, PipMap> &net
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auto input_port_name = input_port_map.find(ctx->getWireName(ctx->getPipSrcWire(pip))[1]);
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auto input_port_name = input_port_map.find(ctx->getWireName(ctx->getPipSrcWire(pip))[1]);
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NPNR_ASSERT(input_port_name != input_port_map.end());
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NPNR_ASSERT(input_port_name != input_port_map.end());
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NPNR_ASSERT(cell->ports.find(input_port_name->second) == cell->ports.end());
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cell->addInput(input_port_name->second);
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cell->connectPort(input_port_name->second, ni);
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cell->connectPort(input_port_name->second, ni);
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auto output_port_map =
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auto output_port_map =
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@ -536,7 +541,6 @@ void GateMateImpl::reassign_cplines(NetInfo *ni, const dict<WireId, PipMap> &net
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auto output_port_name = output_port_map.find(ctx->getWireName(ctx->getPipDstWire(pip))[1]);
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auto output_port_name = output_port_map.find(ctx->getWireName(ctx->getPipDstWire(pip))[1]);
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NPNR_ASSERT(output_port_name != output_port_map.end());
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NPNR_ASSERT(output_port_name != output_port_map.end());
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NPNR_ASSERT(cell->ports.find(output_port_name->second) == cell->ports.end());
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NetInfo *new_net =
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NetInfo *new_net =
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ctx->createNet(ctx->idf("%s$%s", cell->name.c_str(ctx), output_port_name->second.c_str(ctx)));
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ctx->createNet(ctx->idf("%s$%s", cell->name.c_str(ctx), output_port_name->second.c_str(ctx)));
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@ -565,9 +569,6 @@ void GateMateImpl::postRoute()
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if (extra_data.type == PipExtra::PIP_EXTRA_MUX && (extra_data.flags & MUX_ROUTING)) {
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if (extra_data.type == PipExtra::PIP_EXTRA_MUX && (extra_data.flags & MUX_ROUTING)) {
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nets_with_bridges.insert(ni->name);
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nets_with_bridges.insert(ni->name);
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}
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}
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if (extra_data.type == PipExtra::PIP_EXTRA_MUX && (extra_data.mask != 0)) {
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nets_with_cplines.insert(ni->name);
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}
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}
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}
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}
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}
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}
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}
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@ -615,6 +616,18 @@ void GateMateImpl::postRoute()
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num = 0;
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num = 0;
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for (auto &net : ctx->nets) {
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NetInfo *ni = net.second.get();
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for (auto &w : ni->wires) {
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if (w.second.pip != PipId()) {
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const auto &extra_data = *pip_extra_data(w.second.pip);
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if (extra_data.type == PipExtra::PIP_EXTRA_MUX && (extra_data.mask != 0)) {
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nets_with_cplines.insert(ni->name);
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}
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}
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}
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}
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for (auto net_name : nets_with_cplines) {
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for (auto net_name : nets_with_cplines) {
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auto *ni = ctx->nets.at(net_name).get();
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auto *ni = ctx->nets.at(net_name).get();
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auto net_wires = ni->wires; // copy wires to preserve across unbind/rebind.
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auto net_wires = ni->wires; // copy wires to preserve across unbind/rebind.
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